GS8256436GD-200 Datasheet | GSI Technology

GS8256418/36(GB/GD)-400/333/250/200 119- & 165-Bump BGA mercial Temp Industrial Temp 16M x 18, 8M x 36 288Mb DCD Sync Burst SRAMs 400 MHz- 200 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O Features - FT pin for user-configurable flow through or pipeline operation - Single/Dual Cycle Deselect selectable - IEEE 1149.1 JTAG-patible Boundary Scan - ZQ mode pin for user-selectable high/low output drive - 2.5 V +10%/- 10% core power supply - 3.3 V +10%/- 10% core power supply - 2.5 V or 3.3 V I/O supply - LBO pin for Linear or Interleaved Burst mode - Internal input resistors on mode pins allow floating mode pins - Byte Write (BW) and/or Global Write (GW) operation - Internal self-timed write cycle - ZZ pin for automatic power-down - Ro HS-pliant 119-bump and 165-bump BGA packages Functional Description Applications The GS8256418/36 is a 301,989,888-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT...