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GS82564Z36GB Datasheet Preview

GS82564Z36GB Datasheet

Synchronous NBT SRAM

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GS82564Z18/36(GB/GD)-xxxV
119- & 165-Bump BGA
Commercial Temp
Industrial Temp
288Mb Pipelined and Flow Through
Synchronous NBT SRAM
333 MHz200 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
Features
• NBT (No Bus Turn Around) functionality allows zero wait
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 1.8 V or 2.5 V +10%/–10% core power supply
• 1.8 V or 2.5 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 4Mb, 9Mb, 18Mb, 36Mb, and 72Mb
devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• RoHS-compliant 119- and 165-bump BGA packages
Functional Description
The GS82564Z18/36-xxxV is a 288Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS82564Z18/36-xxxV may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS82564Z18/36-xxxV is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump or 165-bump BGA package.
Parameter Synopsis
Pipeline
3-1-1-1
Flow Through
2-1-1-1
tKQ
tCycle
Curr (x18)
Curr (x36)
tKQ
tCycle
Curr (x18)
Curr (x36)
-333 -250 -200 Unit
2.5
2.5
3.0
ns
3.0
4.0
5.0
ns
630 520 450 mA
690 570 490 mA
4.5
5.5
6.5
ns
4.5
5.5
6.5
ns
490 430 400 mA
530 470 440 mA
Rev: 1.02a 8/2017
1/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology




GSI Technology

GS82564Z36GB Datasheet Preview

GS82564Z36GB Datasheet

Synchronous NBT SRAM

No Preview Available !

GS82564Z18/36(GB/GD)-xxxV
GS82564Z36GB Pad Out–119-Bump BGA—Top View
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
A
VDDQ
A
B
NC
E2
A
ADV
A
E3
NC
B
C
NC
A
A
VDD
A
A
NC
C
D
DQC DQPC
VSS
ZQ
VSS
DQPB
DQB
D
E
DQC
DQC
VSS
E1
VSS
DQB
DQB
E
F
VDDQ
DQC
VSS
G
VSS
DQB
VDDQ
F
G
DQC
DQC
BC
A
BB
DQB
DQB
G
H
DQC
DQC
VSS
W
VSS
DQB
DQB
H
J
VDDQ
VDD
NC
VDD
NC
VDD
VDDQ
J
K
DQD
DQD
VSS
CK
VSS
DQA
DQA
K
L
DQD
DQD
BD
NC
BA
DQA
DQA
L
M
VDDQ
DQD
VSS
CKE
VSS
DQA
VDDQ
M
N
DQD
DQD
VSS
A1
VSS
DQA
DQA
N
P
DQD DQPD
VSS
A0
VSS
DQPA
DQA
P
R
A
A
LBO
VDD
FT
A
A
R
T
NC
A
A
A
A
A
ZZ
T
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
U
7 x 17 Bump BGA—14 x 22 mm2 Body—1.27 mm Bump Pitch
Rev: 1.02a 8/2017
2/32
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology



Part Number GS82564Z36GB
Description Synchronous NBT SRAM
Maker GSI Technology
Total Page 3 Pages
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