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GS82582DT39GE Datasheet Preview

GS82582DT39GE Datasheet

288Mb SigmaQuad-II+ Burst of 4 SRAM

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165-Bump BGA
Commercial Temp
Industrial Temp
GS82582DT21/39GE-675S/633S/550S
288Mb SigmaQuad-II+
Burst of 4 SRAM
Up to 675 MHz
1.8 V VDD
1.5 V I/O
Features
• For use with GSI FPGA-based Controller IP
• 3.0 Clock Latency
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• Dual-Range On-Die Termination (ODT) on Data (D), Byte
Write (BW), and Clock (K, K) inputs
• 1.8 V +100/–100 mV core power supply
• 1.5 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• Data Valid Pin (QVLD) Support
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• 6/6 RoHS-compliant 165-bump BGA package
SigmaQuadFamily Overview
The GS82582DT21/39GE are built in compliance with the
SigmaQuad-II+ SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 301,989,888-bit (288Mb)
SRAMs. The GS82582DT21/39GE SigmaQuad SRAMs are
just one element in a family of low power, low voltage HSTL
I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS82582DT21/39GE SigmaQuad-II+ SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer.
Each internal read and write operation in a SigmaQuad-II+ B4
RAM is four times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore the address
field of a SigmaQuad-II+ B4 RAM is always two address pins
less than the advertised index depth (e.g., the 16M x 18 has a
4M addressable index).
tKHKH
Parameter Synopsis
-675S
1.48 ns
-633S
1.58 ns
-550S
1.81 ns
Rev: 1.01 4/2016
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology




GSI Technology

GS82582DT39GE Datasheet Preview

GS82582DT39GE Datasheet

288Mb SigmaQuad-II+ Burst of 4 SRAM

No Preview Available !

GS82582DT21/39GE-675S/633S/550S
8M x 36 SigmaQuad-II+ SRAM—Top View
1 2 3 4 5 6 7 8 9 10
A CQ SA SA W BW2 K BW1 R SA SA
B Q27 Q18 D18 SA BW3 K BW0 SA D17 Q17
C D27 Q28 D19 VSS SA NC SA VSS D16 Q7
D D28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
G
D30
D22
Q22 VDDQ VDD
VSS
VDD
VDDQ
Q13
D13
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
K
Q32 D32 Q23 VDDQ VDD
VSS
VDD
VDDQ
Q12
D3
L
Q33
Q24
D24 VDDQ VSS
VSS
VSS
VDDQ
D11
Q11
M D33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1
N
D34 D26 Q25 VSS SA
SA
SA
VSS Q10
D9
P
Q35 D35 Q26
SA
SA QVLD SA
SA
Q9
D0
R
TDO TCK
SA
SA
SA ODT SA
SA
SA TMS
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Note:
BW0 controls writes to D0:D8; BW1 controls writes to D9:D17; BW2 controls writes to D18:D26; BW3 controls writes to D27:D35
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
Rev: 1.01 4/2016
2/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology


Part Number GS82582DT39GE
Description 288Mb SigmaQuad-II+ Burst of 4 SRAM
Maker GSI Technology
Total Page 27 Pages
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