GSI Technology GS8342T18BD
The GS8342T08/09/18/36BD are built in compliance with the SigmaDDR-II SRAM pinout standard for Common I/O sync| Part No. | GS8342T18BD |
|---|---|
| Datasheet | GS8342T18BD Download |
| Manufacturer |  GSI Technology |
| Description | 36Mb SigmaDDR-II Burst of 2 SRAM |
| Buy | Stock & Price |
FEATURES
● Simultaneous Read and Write SigmaDDR™ Interface● Common I/O bus
● JEDEC-standard pinout and package
● Double Data Rate interface
● Byte Write (x36, x18 and x9) and Nybble Write (x8) function
● Burst of 2 Read and Write
● 1.8 V +100/–100 mV core power supply
● 1.5 V or 1.8 V HSTL Interface
● Pipelined read operation with self-timed Late Write
● Fully coherent read and write pipelines
● ZQ pin for programmable output drive strength
● IEEE 1149.1 JTAG-compliant Boundary Scan
● Pin-compatible with present 9Mb, 18Mb, 36Mb and 72Mb devices
● 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
● RoHS-compliant 165-bump BGA package available SigmaDDR™ Family Overview
