GSI Technology GS8662DT20BD
The GS8662DT06/11/20/38BD are built in compliance with the SigmaQuad-II+ SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. The GS8662DT06/11/20/38BD SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.| Part No. | GS8662DT20BD |
|---|---|
| Datasheet | GS8662DT20BD Download |
| Manufacturer |  GSI Technology |
| Description | 72Mb SigmaQuad-II+ Burst of 4 SRAM |
| Buy | Stock & Price |
FEATURES
● 2.5 Clock Latency● Simultaneous Read and Write SigmaQuad™ Interface
● JEDEC-standard pinout and package
● Dual Double Data Rate interface
● Byte Write controls sampled at data-in time
● Burst of 4 Read and Write
● Dual-Range On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) intputs
● 1.8 V +100/–100 mV core power supply
● 1.5 V or 1.8 V HSTL Interface
● Pipelined read operation
● Fully coherent read and write pipelines
● ZQ pin for programmable output drive strength
● Data Valid Pin (QVLD) Support
● IEEE 1149.1 JTAG-compliant Boundary Scan
● 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
● RoHS-compliant 165-bump BGA package available SigmaQuad-II™ Family Overview They are 75,497,472-bit (72Mb) SRAMs. Clocking and Addressing Schemes The GS8662DT06/11/20/38BD SigmaQuad-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer.
