GS8672D19BGE
Features
- 2.0 Clock Latency
- On-Chip ECC with virtually zero SER
- Simultaneous Read and Write Sigma Quad™ Interface
- JEDEC-standard pinout and package
- Dual Double Data Rate interface
- Byte Write Capability due to ECC
- Burst of 4 Read and Write
- On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) outputs
- 1.8 V +100/- 100 m V core power supply
- 1.5 V HSTL Interface
- Pipelined read operation
- Fully coherent read and write pipelines
- ZQ pin for programmable output drive strength
- IEEE 1149.1 JTAG-pliant Boundary Scan
- Pin-patible with 18Mb, 36Mb and 144Mb devices
- 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
- Ro HS-pliant 165-bump BGA package available
Sigma Quad™ ECCRAM Overview
The GS8672D19/37BE are built in pliance with the Sigma Quad-II+ ECCRAM pinout standard for Separate I/O synchronous ECCRAMs. They are 75,497,472-bit (72Mb) ECCRAMs. The GS8672D19/37BE Sigma Quad ECCRAMs are just one element in a family of low power, low voltage HSTL I/O...
