* 2.0 Clock Latency
* On-Chip ECC with virtually zero SER
* Simultaneous Read and Write SigmaQuad™ Interface
* JEDEC-standard pinout and package
* Dua.

where alternating reads and writes are needed. Therefore, the SigmaQuad-II+ ECCRAM interface and truth table are optimiz.

Table Symbol Description Type Comments SA Synchronous Address Inputs Input — R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0
  –BW3 Synchronous Byte Writes Input Active Low K Input Clock Inp.

+

GS8672D19BE

GS8672D18BE

GS8672D36BE

GS8672D37BE

GS8672D37BGE

GS8672T20BE

GS8672T20BGE

GS8672T38BE

GS8672T38BGE

GS8673ED18BGK

GS8673ED18BK

GS8673ED36BGK

GS8673ED36BK