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Gennum

GS2961 Datasheet Preview

GS2961 Datasheet

Receiver

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GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer
complete with SMPTE Video Processing
Key Features
• Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s,
1.485/1.001Gb/s and 270Mb/s
• Supports SMPTE 425M (Level A and Level B), SMPTE
424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
• Integrated adaptive cable equalizer
• Typical equalized length of Belden 1694A cable:
Š 150m at 2.97Gb/s
Š 250m at 1.485Gb/s
Š 480m at 270Mb/s
• Integrated Reclocker with low phase noise, integrated
VCO
• Serial digital reclocked, or non-reclocked output
• Ancillary data extraction
• Optional conversion from SMPTE 425M Level B to
Level A for 1080p 50/60 4:2:2 10-bit
• Parallel data bus selectable as either 20-bit or 10-bit
• Comprehensive error detection and correction
features
• Output H, V, F or CEA 861 Timing Signals
• 1.2V digital core power supply, 1.2V and 3.3V analog
power supplies, and selectable 1.8V or 3.3V I/O power
supply
• GSPI Host Interface
• -20ºC to +85ºC operating temperature range
• Low power operation (typically 515mW)
• Small 11mm x 11mm 100-ball BGA package
• Pb-free and ROHS compliant
Errata
Refer to Errata document entitled GS2960/GS2961 Errata
for this device (document number 53117).
Applications
Application: Single Link (3G-SDI)
to Dual Link (HD-SDI) Converter
3G-SDI
GS2961
10-bit
HV F/PCLK
HV F/PCLK
10-bit
GS2962
GS2962
HD-SDI
Link A
HD-SDI
Link B
HD-SDI
Link A
HD-SDI
Link B
Application: Dual Link (HD-SDI)
to Single Link (3G-SDI) Converter
HD-SDI
Deserializer
GS2961
10-bit
HV F/PCLK
FIFO
WR
HD-SDI
Deserializer
GS2961
10-bit
HV F/PCLK
FIFO
WR
10-bit
HV F/PCLK
10-bit
GS2962
3G-SDI
GS4910
HVF
X TAL
Description
The GS2961 is a multi-rate SDI integrated Receiver which
includes complete SMPTE processing, as per SMPTE 425M,
292M and SMPTE 259M-C. The SMPTE processing features
can be bypassed to support signals with other coding
schemes.
The GS2961 integrates Gennum's adaptive cable equalizer
technology, achieving unprecedented cable lengths and
jitter tolerance. It features DC restoration to compensate for
the DC content of SMPTE pathological signals.
The device features an Integrated Reclocker with an
internal VCO and a wide Input Jitter Tolerance (IJT) of
0.7UI.
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
www.gennum.com
1 of 104




Gennum

GS2961 Datasheet Preview

GS2961 Datasheet

Receiver

No Preview Available !

A serial digital loop-through output is provided, which can
be configured to output either reclocked or non-reclocked
serial digital data. The serial digital output can be connected
to an external cable driver.
The device operates in one of four basic modes: SMPTE
mode, DVB-ASI mode, Data-Through mode or Standby
mode.
In SMPTE mode (the default operating mode), the GS2961
performs full SMPTE processing, and features a number of
data integrity checks and measurement capabilities.
The device also supports ancillary data extraction, and can
provide entire ancillary data packets through
host-accessible registers. It also provides a variety of other
packet detection and error handling features. All of these
processing features are optional, and may be individually
enabled or disabled through register programming.
Both SMPTE 425M Level A and Level B inputs are supported
with optional conversion from Level B to Level A for 1080p
50/59.94/60 4:2:2 10-bit inputs.
In DVB-ASI mode, sync word detection, alignment and
8b/10b decoding is applied to the received data stream.
In Data-Through mode all forms of SMPTE and DVB-ASI
processing are disabled, and the device can be used as a
simple serial to parallel converter.
The device can also operate in a lower power Standby
mode. In this mode, no signal processing is carried out and
the parallel output is held static.
Parallel data outputs are provided in 20-bit or 10-bit format
for 3Gb/s, HD and SD video rates, with a variety of mapping
options. As such, this parallel bus can interface directly with
video processor ICs, and output data can be multiplexed
onto 10 bits for a low pin count interface.
Functional Block Diagram
VBG
LB_CONT
LF
SDI
SDI
AGC+
AGC-
SDO
SDO
Crystal
Buffer/
Oscillator
GSPI and
JTAG Controller
Host
Interface
EQ
Buffer
Reclocker
with
Integrated
VCO
Serial
to
Parallel
Converter
Descramble,
Word Align,
Rate Detect
Flywheel
Video
Standard
Detect
TRS
Detect
Timing
Extraction
ANC/
Checksum
/352M
Extraction
SMPTE 425M
Level B Level A
1080p 50/60
4:2:2 10-bit
Illegal code
remap,
TRS/
Line Number/
CRS
Insertion,
EDH Packet
Mux
Output Mux/
Demux
Insertion
Buffer
Mux
DVB-ASI
Decoder
I/O Control
PCLK
DOUT[19:0]
LOCKED
GS2961 Functional Block Diagram
GS2961 3Gb/s, HD, SD SDI Receiver, with Integrated
Adaptive Cable Equalizer
Data Sheet
48004 - 2
November 2009
2 of 104


Part Number GS2961
Description Receiver
Maker Gennum
Total Page 30 Pages
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