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HI-6130 - 3.3V BC / MT / RT Multi-Terminal Device

Description

The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus.

Each IC contains a Bus Controller (BC), a Bus Monitor Terminal (MT) and two independent Remote Terminals (RTs).

Features

  • Concurrent multi-terminal operation for one to four MIL-STD-1553B functions: BC, MT and two independent RTs.
  • 64K bytes internal static RAM with RAM Error Detection/Correction option.
  • Autonomous terminal operation requires minimal host intervention.
  • Shared MIL-STD-1553 bus interface reduces circuit complexity and circuit board area. RT1ENA - 26 A3 - 27 A4 - 28 A5 - 29 RT1AP - 30 MISO - 31 MOSI - 32 A6 - 33 A7 - 34 A8 - 35 VCC - 36 GND - 37 TTCLK - 38 MTTCL.

📥 Download Datasheet

Datasheet Details

Part number HI-6130
Manufacturer HOLTIC
File Size 3.67 MB
Description 3.3V BC / MT / RT Multi-Terminal Device
Datasheet download datasheet HI-6130 Datasheet

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Other Datasheets by HOLTIC

Part Number Description
HI-6131 3.3V BC / MT / RT Multi-Terminal Device
HI-6132 3.3V BC / MT / RT Multi-Terminal Device
HI-6135 Compact Remote Terminal
HI-6136 Compact Multi-Terminal Device
HI-6137 Compact Multi-Terminal Device

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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October, 2016 HI-6130 / HI-6131 / HI-6132 MIL-STD-1553 / MIL-STD-1760 3.3V BC / MT / RT Multi-Terminal Device GENERAL DESCRIPTION The 3.3V CMOS HI-613x device provides a complete single- or multi-function interface between a host processor and MIL-STD-1553B bus. Each IC contains a Bus Controller (BC), a Bus Monitor Terminal (MT) and two independent Remote Terminals (RTs). Any combination of the contained 1553 functions can be enabled for concurrent operation. The enabled terminals communicate with the MIL-STD-1553 buses through a shared on-chip dual bus transceiver and external transformer. The user allocates 64K bytes of on-chip static RAM between devices to suit application requirements.
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