HI-6130
Description
The 3.3V CMOS HI-613x device provides a plete single- or multi-function interface between a host processor and MIL-STD-1553B bus.
Key Features
- Concurrent multi-terminal operation for one to four MIL-STD-1553B functions: BC, MT and two independent RTs
- 64K bytes internal static RAM with RAM Error Detection/Correction option
- Autonomous terminal operation requires minimal host intervention
- Shared MIL-STD-1553 bus interface reduces circuit plexity and circuit board area
- Fully programmable Bus Controller with 28 op code instruction set
- Simple Monitor Terminal (SMT) Mode records mands and data separately, with 16-bit or 48bit time tagging
- IRIG Monitor Terminal (IMT) Mode supports IRIG106 Chapter 10 packet format
- 64-Word Interrupt Log Buffer queues the most recent 32 interrupts. Hardware-assisted interrupt decoding quickly identifies interrupt sources
- Built-in self-test for protocol logic, digital signal paths and internal RAM
- Optional self-initialization at reset uses external serial EEPROM
