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HDMP-1514 Datasheet Preview

HDMP-1514 Datasheet

Fibre Channel Transmitter and Receiver Chipset

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Fibre Channel Transmitter and
Receiver Chipset
Technical Data
HDMP-1512 Transmitter
HDMP-1514 Receiver
Features
• ANSI X3.230-1994 Fibre
Channel Standard
Compatible (FC-0)
• Selectable 531.25 Mbaud or
1062.5 Mbaud Data Rates
• Selectable On Chip Laser
Driver and 50 Cable
Driver
• TTL Compatible I/Os
• Single +5.0 V Power Supply
Applications
• Mass Storage System I/O
Channel
• Work Station/Server I/O
Channel
• High Speed Peripheral
Interface
Description
The HDMP-1512 transmitter and
the HDMP-1514 receiver are
bipolar integrated circuits,
separately packaged, in 80 pin M-
Quad packages. They are used to
build a high speed Fibre Channel
link for point to point data com-
munications. Shown in Figure 1 is
a typical full duplex point-to-
point Fibre Channel link. The
sending system provides parallel,
8B/10B, encoded data and a
transmit byte clock to the HDMP-
1512 transmitter. Using the trans-
mit byte clock, the transmitter
converts the data to a serial
stream and sends it over a copper
cable or fiber-optic link. The
receiver converts the serial data
stream back to parallel encoded
data and presents it, along with
the recovered transmit byte
clock, to the receiving system.
The sending system has the
option to electrically wrap the
transmitted data back to the local
receiver. It is possible to transmit
over the cable driver, or laser
driver when data is being
wrapped back to the local
receiver.
The two-chip set (transmitter
chip and receiver chip) is
compatible with the FC-0 layer of
the American National Standards
Institute (ANSI), Fibre Channel
specification, X3.230-1994. This
specification defines four
standard rates of operation for
Fibre Channel links. The HDMP-
1512 and HDMP-1514 chip-set
will operate at the two highest
defined serial rates of 531.25
Mbaud and 1062.5 Mbaud. These
serial baud rates correspond to
8B/10B encoded byte rates of 50
Mbytes/sec and 100 Mbytes/sec
respectively. The proper setting
of a single pin on each chip
selects the desired rate of
operation.
Several features, exclusive to this
chip-set, make it ideal for use in
Fibre Channel links. In addition,
the laser driver on the transmitter
chip, the dual loss of light
detectors on the receiver chip,
and the power supervisor and
power reset features make this
chip-set ideal for use with laser
optics. The serial cable driver
(transmitter chip), and the cable
equalizer (on the receiver chip),
can be operated in conjunction
with, or as an alternative to, the
laser driver. The laser driver can
also be driven directly with an
external high speed serial input.
Altogether, the various features,
input/output options, and
flexibility of this chip-set make
several unique link configurations
possible. In particular, it is ideally
suited for use in applications
where conformance to the FCSI
specification # 301-Rev 1.0,
Gbaud Link Module Specification,
is desired.
656 5964-6637E (4/96)




HP

HDMP-1514 Datasheet Preview

HDMP-1514 Datasheet

Fibre Channel Transmitter and Receiver Chipset

No Preview Available !

CLOCK
ENCODED DATA
Tx SERIAL LINK
Rx
ENCODED DATA
CLOCK
Rx
REF CLOCK
Figure 1. Point-to-Point Data Link.
SERIAL LINK
Tx
REF CLOCK
CLOCK
ENCODED DATA
ENCODED DATA
CLOCK
DATA BYTE 0 10
Tx [00:09]
DATA BYTE 1
TTL INTERFACE
AND
INPUT LATCH
20
FRAME
MULTIPLEXER
Tx [10:19] 10
I/O
SELECT
2
± LOUT
CABLE
DRIVERS
2
± SO
TBC
PLL/CLOCK
GENERATOR
INTERNAL
CLOCKS
LASER
DRIVER
2
± LZOUT
LASER
CONTROLS
Figure 2. HDMP-1512 (Tx) Block Diagram.
Transmitter Operation
The block diagram of the HDMP-
1512 transmitter is shown in
Figure 2. The basic functions of
the transmitter chip are the TTL
Interface and Input Latch, Frame
Multiplexing, Input/Output
selection, cable drivers, Laser
Driver, and monolithic Phase
Locked loop clock generator. The
actual operation of each function
changes slightly, according to the
desired configuration and option
settings. Figures 18 and 19 show
schematically how to terminate
each pin on the HDMP-1512
when used in systems incorporat-
ing either copper or fiber media.
There are two main modes of
operation for the transmitter
chip, both are based on the
selected baud rate. The baud rate
is controlled by the appropriate
setting of the SPDSEL pin, #67.
When this pin is set low, the
transmitter operates at a serial
rate of 531.25 Mbaud. When pin
#67 is set high the transmitter
operates at a serial rate of 1062.5
Mbaud. As such, the two main
modes of operation are the
531.25 Mbaud mode and the
1062.5 Mbaud mode.
The transmitter does not encode
the applied data. It assumes the
data is pre-encoded using the
8B/10B encoding scheme as
defined in ANSI X3.230-1994.
The TTL input interface receives
data at the standard TTL levels
specified in the dc Electrical
Specification table. The internal
phase locked loop (PLL) locks to
the transmit byte clock, TBC.
TBC is supplied to the transmitter
chip by the sending system. TBC
should be a 53.125 MHz clock
(± 100 ppm) as defined in
X3.230-1994. Once the PLL has
locked to TBC, all the clocks used
by the transmitter are generated
by the internal clock generator.
657


Part Number HDMP-1514
Description Fibre Channel Transmitter and Receiver Chipset
Maker HP
Total Page 26 Pages
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