SEMICONDUCTOR
DG200, DG201
December 1993
CMOS Dual/Quad SPST Analog Switches
Features
Description
• Switches Greater than 28VP-P Signals with ±15 Supplies
• Break-Before-Make Switching tOFF 250ns, tON 700ns
Typical
• TTL, DTL, CMOS, PMOS Compatible
• Non-Latching with Supply Turn-Off
• Complete Monolithic Construction
• Industry Standard (DG200, DG201)
The DG200 and DG201 solid state analog gates are
designed using an improved, high voltage CMOS monolithic
technology. They provide ease-of-use and performance
advantages not previously available from solid state
switches. Destructive latch-up of solid state analog gates
has been eliminated by Harris's CMOS technology.
The DG200 and DG201 are completely specification and
pinout compatible with the industry standard devices.
Applications
• Data Acquisition
• Sample and Hold Circuits
• Operational Amplifier Gain Switching Networks
Ordering Information
PART NUMBER
DG200AA
DG200AK
DG200BA
DG200BK
DG200CJ
DG200AA/883B
DG200AK/883B
DG201AK
DG201BK
DG201CJ
DG201AK/883B
TEMPERATURE
-55oC to +125oC
-55oC to +125oC
-25oC to +85oC
-25oC to +85oC
0oC to +70oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
-25oC to +85oC
0oC to +70oC
-55oC to +125oC
PACKAGE
10 Pin Metal Can
14 Lead Ceramic DIP
10 Pin Metal Can
14 Lead Ceramic DIP
14 Lead Plastic DIP
10 Pin Metal Can
14 Lead Ceramic DIP
16 Lead Ceramic DIP
16 Lead Ceramic DIP
16 Lead Plastic DIP
16 Lead Ceramic DIP
Pinouts
DG200
(CDIP, PDIP)
TOP VIEW
IN2 1
NC 2
GND 3
NC 4
S2 5
D2 6
V- 7
14 IN1
13 NC
12 V+ (SUBSTRATE)
11 NC
10 S1
9 D1
8 VREF
DG200
(TO-100 METAL CAN)
TOP VIEW
V+
(SUBSTRATE AND CASE)
10
IN1 1
9 S1
IN2 2
8 D1
GND 3
S2 4
7 VREF
5 6 V-
D2
IN1 1
D1 2
S1 3
V- 4
GND 5
S4 6
D4 7
IN4 8
DG201
(CDIP, PDIP)
TOP VIEW
16 IN2
15 D2
14 S2
13 V+(SUBSTRATE)
12 VREF
11 S3
10 D3
9 IN3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1993
9-13
File Number 3115
