74HC95 Datasheet | Hitachi Semiconductor

.. HD74HC95 4-bit Parallel Access Shift Register Description This 4-bit register Features parallel and serial inputs, parallel outputs, mode control, and two clock inputs. The register has three mode operation: - Parallel (broadside) load - Shift right (the direction Q A toward QD) - Shift left (the direction QD toward QA) Parallel loading is acplished by applying the four bits of data and taking the mode conrol input high. The data is loaded into the associated flip-flops and appears at the outputs after the high-to-low transition of the clock-2 input. During loading, the entry of serial data is inhibited. Shift right is acplished on the high-to-low transition of clock-1 when the mode control is low; shift left is acplished on the high-tolow transition of clock-2 when the mode control is high by connecting the output of each flip-flop (Q D to input C, etc.) and serial data is entered at input D. The clock input may be applied monly to clock-1 and clock-2 if both modes can be clocked from the same source. Changes at the mode control input should normally be made while both clock inputs are low: however, conditions described in the last three lines of the function table will also ensure that register contents are protected. Features - - - - - High Speed Operation: tpd (Clock to Q) = 17 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC95 .. Function Table Inputs Clocks Mode Control 2 (L) H H H L L L L X X L L L H H L L H L H H 1 (R) X X X H Serial X X X X H L X X X X X Parallel A X a QB+ X X X X X X X X B X b QC+ X X X X X X X X C X c QD+ X X X X X X X X D X d d X X X X X X X X Outputs QA QA0 a QBn QA0 H L QA0 QA0 QA0 QA0 QA0 QB QB0 b QCn QB0 QAn QAn QB0 QB0 QB0 QB0 QB0 QC QC0 c QDn QC0 QBn QBn QC0 QC0 QC0 QC0 QC0 QD QD0 d d QD0 QCn QCn QD0 QD0 QD0 QD0 QD0 Pin...