Figure 2.16(2) H8/3801 Memory Map Figure 2.16(3) H8/3800 Memory Map Table 3.2 Interrupt Sources and Their Priorities Table 3.3 Interrupt Control Registers Description Des.

Description of time specification amended Figure amended Figure amended Amended Initial values amended 1. IRQ edge select register (IEGR) Bits 4 to 2 amended 62 63 to 65 65 67, 68 3.3.5 Interrupt Operations 3.4.2 Notes on Rewriting Port Mode Registe.

HD6433800

HD6433800FP

HD6433800H

HD6433800P

HD6433801

HD6433801FP

HD6433801H

HD6433801P

HD6433802FP

HD6433802H

HD6433802P

HD6433822

HD6433823