bcd-to-seven segment latch/decoder/driver.
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* High Speed Operation: tpd (A, B, C, D to a
– g) = 33 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide .
This circuit contains a 4-bit latch, BCD-to-7 segment decoder, and 7 outpt drivers. Data on the input pins flow through to the output when the Latch Disable (LE) is high and is latched on the high to low transition of the LE input. The Phase input (P.
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