HD74HCT244
Description
The HD74HCT244 is a non-inverting buffer and has two active low enable (1G and 2G ). Each enable independently controls 4 buffers. This device does not have schmitt trigger inputs.
Features
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- - LSTTL Output Logic Level patibility as well as CMOS Output patibility High Speed Operation: tpd (A to Y) = 10 ns typ (CL = 50 p F) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs G H L L H L X Z : : : : A X H L High level Low level Irrelevant Off (high-impedance) state of a 3-state output Output Y Z H L
Pin Arrangement
1G 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1
1 2 3 4 5 6 7 8 9
20 VCC 19 2G 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 2A1 (Top view)
GND 10
Block Diagram
To three other inverters VCC One of 8 inverters Input A Y
Strobe G
Absolute Maximum Ratings
Item Supply voltage range...
