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HI-8591 Datasheet Preview

HI-8591 Datasheet

ARINC 429 LINE RECEIVER

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HI-8591 pdf
August 2006
HI-8591
ARINC 429 LINE RECEIVER
DESCRIPTION
The HI-8591 is an ARINC 429 bus interface receiver
designed to operate from a single 3.3 V or 5 V supply. The
part is designed with high-impedance inputs to minimize
bus loading, and has an exceptional input common-mode
performance in excess of +/- 30V, making it immune to
ground offsets around the aircraft. The RINA and RINB
inputs of the standard HI-8591 may be connected directly
to the ARINC 429 bus. To enable external lightning protec-
tion circuitry to be added, the HI-8591-40 variant is avail-
able. The HI-8591-40 requires only the addition of external
40 KW, ¼ watt resistors in series with RINA and RINB to
allow the part to meet the lightning protection requirements
of DO-160D level 3.
The typical 10 volt differential ARINC 429 signal is trans-
lated and input to a window comparator and latch. The
comparator levels are set just below the standard 6.5 volt
minimum ARINC data threshold and just above the stan-
dard 2.5 volt maximum ARINC null threshold.
The TESTA and TESTB inputs bypass the analog inputs for
testingwww.DataSheet4U.com purposes. Also if TESTA and TESTB are both taken
high, the digital outputs are forced to zero.
See Holt Application Note AN-300 for more information on
lightning protection.
FEATURES
! ARINC 429 line receiver interface in a
small outline package
! 3.3V single rail supply voltage
! +/-30 V common-mode performance
! >140 KOhm input impedance
! Lightning protection simplified with the
ability to add 40 KOhm external series
resistors
! Receiver input hysteresis at least 2 volt
! Test inputs bypass analog inputs and
force digital outputs to a one, zero or
null state
PIN CONFIGURATIONS
VCC - 1
TESTA - 2
RINB - 3
RINA - 4
8 - TESTB
7 - ROUTB
6 - ROUTA
5 - GND
HI-8591PSI, HI-8591PST & HI-8591PSM
HI-8591PSI-40, HI-8591PST-40 & HI-8591PSM-40
8 - PIN PLASTIC NARROW BODY SOIC
TESTA 1
RINB 2
RINA 3
NC 4
12 ROUTB
11 NC
10 ROUTA
9 NC
HI-8591PCI, HI-8591PCT, HI-8591PCI-40 & HI-8591PCT-40
16- pin 4mm x 4mm Chip-scale package
SUPPLY VOLTAGES
vcc = 3.3V ± 10%, 5.0V ± 10%
FUNCTION TABLE
RINA
-1.25V to 1.25V
-3.25V to -6.5V
3.25V to 6.5V
X
X
X
RINB
-1.25V to 1.25V
3.25V to 6.5V
-3.25V to -6.5V
X
X
X
TESTA
0
0
0
0
1
1
TESTB ROUTA ROUTB
0 00
0 01
0 10
1 01
0 10
1 00
PIN DESCRIPTION TABLE
SYMBOL
VCC
TESTA
RINB
RINA
GND
ROUTA
ROUTB
TESTB
FUNCTION
SUPPLY
LOGIC INPUT
ARINC INPUT
ARINC INPUT
POWER
LOGIC OUTPUT
LOGIC OUTPUT
LOGIC INPUT
DESCRIPTION
3.3V or 5V SUPPLY
CMOS
RECEIVER B INPUT
RECEIVER A INPUT
GROUND
RECEIVER CMOS OUTPUT A
RECEIVER CMOS OUTPUT B
CMOS
(DS8591, Rev. D)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/06



Holt Integrated Circuits
Holt Integrated Circuits

HI-8591 Datasheet Preview

HI-8591 Datasheet

ARINC 429 LINE RECEIVER

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HI-8591 pdf
HI-8591
FUNCTIONAL DESCRIPTION
RECEIVER
Figure 1 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each require 140KW of resis-
tance between the ARINC bus and comparator. This resis-
tance is completely on-chip for the HI-8591. In contrast,
the HI-8591-40 has 100 KW on-chip and requires an exter-
nal 40KW, ¼ watt resistor on each of the ARINC 429 input
pins. The HI-8591-40 device is typically chosen for appli-
cations where lightning protection is a requirement.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the differ-
ential signal is compared to levels derived from a divider
between V.C. and Ground. The nominal settings corre-
spond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins. If TESTA and TESTB are both One, the HI-
8591 outputs are pulled low. This allows the digital out-
puts of a transmitter to be connected to the test inputs
through control logic for system self-test purposes.
RINA
RINB
ESD
PROTECTION
AND
TRANSLATION
ONE
NULL
ZERO
NULL
SQ
LATCH
R
TEST
TESTA
TESTB
SQ
LATCH
R
TEST
TESTA
TESTB
FIGURE 1 - RECEIVER BLOCK DIAGRAM
ROUTA
ROUTB
HARDWIRE
OR
{
DRIVE FROM LOGIC
APPLICATION INFORMATION
Figure 2 shows a possible application of the
HI-8591 interfacing an ARINC 429 bus input
to a 3.3V ASIC or FPGA. In this example a
HI-8586 ARINC 429 line driver is used to
take 3.3V logic outputs and generate the nec-
essary 10V differential signal for driving an
ARINC 429 bus.
ARINC
Channel
ARINC
Channel
3.3V
1
2
VCC
TESTA
ROUTA
6
8
TESTB
7
ROUTB
4 HI-8591
RINA
3
RINB GND
5
15V
18
SLP1.5 V+
6 TXAOUT
3
TX1IN
7
HI-8586
TXBOUT
TX0IN
2
GND V-
45
-15V
FIGURE 2 - APPLICATION DIAGRAM
RXD1
RXD0
FPGA
TXD1
TXD0
HOLT INTEGRATED CIRCUITS
2


Part Number HI-8591
Description ARINC 429 LINE RECEIVER
Maker Holt Integrated Circuits
Total Page 7 Pages
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