HY27UG088G5B
Key Features
- Cost effective solutions for mass storage applications MULTIPLANE ARCHITECTURE
- Array is split into two independent planes. Parallel Operations on both planes are available, halving Program and erase time. NAND INTERFACE
- x8 bus width
- Address/ Data Multiplexing
- Pinout patiblity for all densities SUPPLY VOLTAGE
- 3.3V device : Vcc = 2.7 V ~3.6 V MEMORY CELL ARRAY
- bytes x 64 pages x 8192 blocks PAGE SIZE
- (2K + 64 spare) Bytes BLOCK SIZE
- (128K + 4Kspare) Bytes PAGE READ / PROGRAM
- Random access : 25us (max.)
