HYMP532S64CLP6-S5
FEATURES
- JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are patible with SSTL_1.8 interface Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & CK)
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- Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM DDR2 SDRAM Package: 60ball(x8), 84ball(x16) FBGA 67.60 x 30.00 mm form factor Lead-free Products are Ro HS pliant
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- ORDERING INFORMATION
Part Name HYMP532S64CP6-E3/C4/Y5/S5/S6 HYMP564S64CP6-E3/C4/Y5/S5/S6 HYMP512S64CP8-E3/C4/Y5/S5/S6 HYMP532S64CLP6-E3/C4/Y5/S5/S6 HYMP564S64CLP6-E3/C4/Y5/S5/S6 HYMP512S64CLP8-E3/C4/Y5/S5/S6 Density 256MB 512MB 1GB 256MB 512MB 1GB Organization 32Mx64 64Mx64 128Mx64 32Mx64 64Mx64 128Mx64 # of DRAMs 4 8 16 4 8 16 # of ranks 1 2 2 1 2 2...
