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H55S5132EFR-A3M - 512Mbit (16Mx32bit) Mobile SDR Memory

This page provides the datasheet information for the H55S5132EFR-A3M, a member of the H55S5122EFR 512Mbit (16Mx32bit) Mobile SDR Memory family.

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

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Datasheet Details

Part number H55S5132EFR-A3M
Manufacturer Hynix Semiconductor
File Size 949.60 KB
Description 512Mbit (16Mx32bit) Mobile SDR Memory
Datasheet download datasheet H55S5132EFR-A3M Datasheet
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Full PDF Text Transcription

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512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O Specification of 512M (16Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Sep. 2010 1 il;o;nar 512Mbit (16Mx32bit) Mobile SDR Memory H55S5122EFR Series / H55S5132EFR Series Document Title 4Bank x 4M x 32bits Synchronous DRAM Revision History Revision No. History Draft Date Remark 1.0 1.1 1.2 - First Version Release - Add AC Overshoot/Undershoot Specification - Correction Feb. 2010 Feb. 2010 Sep. 2010 Rev 1.2 / Sep.
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