*
*
*
*
*
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* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) .

which requires large memory density and high bandwidth. This Hynix 256Mb DDR SDRAMs offer fully synchronous operations r.

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Sep. 2009 1 www.DataSheet4U.com H5DU2562GTR H5DU2582GTR Revision History Revi.

H5DU2562GFR

H5DU2582GTR

H5DU1262GTR

H5DU5162EFR

H5DU5162ETR

H5DU5182EFR

H5DU5182ETR

H5DU6462CTR

H5004

H5004NL

H5007

H5007NL

H5008NL