H5MS1222EFP Description
and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied.
H5MS1222EFP Key Features
- Double data rate architecture: two data transfer per clock cycle Mobile DDR SDRAM INTERFACE
- x32 bus width: HY5MS5B2ALFP
- Multiplexed Address (Row address and Column address) BURST LENGTH SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V MEMORY CELL ARRAY
- 128Mbit (x32 device) = 1M x 4Bank x 32 I/O DATA STROBE
- x32 device: DQS0 ~ DQS3
- Bidirectional, data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- Data and data mask referenced to both edges of DQS LOW POWER FEATURES
- PASR (Partial Array Self Refresh)
- AUTO TCSR (Temperature pensated Self Refresh)