SUMMARY
* Mobile DDR SDRAM - Double data rate architecture: two data transfer per clock cycle
* Mobile DDR SDRAM INTERFACE - x32 bus width - Multiplexed Address (.

which use the battery such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-n.

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Jul. 2008 1 www.DataSheet4U.net 11 Mobile DDR SDRAM 512Mbit (16M x 32bit) H5MS5122DFR Series .

H5MS5132DFR

H5MS1222EFP

H5MS1262EFP

H5MS1G22MFP

H5MS1G32MFP

H5MS2532JFR

H5MS2562JFR

H5MS2562JFR-E3M

H5MS2562JFR-J3M

H5MS2562JFR-K3M

H5MS2562JFR-L3M

H5MS2622JFR

H5004