H5TC1G83TFR-xxA Key Features
- VDD=VDDQ=1.35V + 0.100 /
- 0.067V
- Fully differential clock inputs (CK, CK) operation
- 8banks
- Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
- 7.8 µs at 0oC ~ 85 oC
- 3.9 µs at 85oC ~ 95 oC
- Auto Self Refresh supported
- JEDEC standard 78ball FBGA(x4/x8)
- Driver strength selected by EMRS