H5TC8G63AMR-xxA SK Hynix Datasheet

H5TC8G63AMR-xxA Key Features

• VDD=VDDQ=1.35V + 0.100 /
• 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• Average Refresh Cycle (Tcase of 0 oC~ 95 oC)
• 7.8 µs at 0oC ~ 85 oC
• 3.9 µs at 85oC ~ 95 oC
• On chip DLL align DQ, DQS and DQS transition with CK 
• JEDEC standard 78ball FBGA(x4/x8), 96bal FBGA(x16) transition
• Driver strength selected by EMRS