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SK Hynix Electronic Components Datasheet

HMP512F7FFP8C-xx Datasheet

240pin Fully Buffered DDR2 SDRAM DIMMs

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240pin Fully Buffered DDR2 SDRAM DIMMs based on 512 Mb F-ver.
This Hynix’s Fully Buffered DIMM is a high-bandwidth & large capacity channel solution that has a narrow
host interface. Hynix’s FB-DIMM features novel architecture including the Advanced Memory Buffer that
isolates the DDR2 SDRAMs from the channel. This single component located in the front side center of
each DIMM, acts as a repeater and buffer for all signals and commands which are exchanged between the
host controller and the DDR2 SDRAMs including data in and output. The AMB communicates with the host
controller and adjacent DIMMs on a system board using an industry standard Differential Point to Point
Link Interface at 1.5V power.
The AMB also allows buffering of memory traffic to support large memory capacities. All memory control
for the DDR2 SDRAM devices resides in the host, including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access and power management. The AMB interface is responsible for
handling channel and memory requests to and from the local FBDIMM and for forwarding request to other
FBDIMMs on the memory channel.
FEATURES
• 240 pin Fully Buffered ECC dual In-Line DDR2 SDRAM Module
• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 interface
• Built with 512Mb DDR2 SDRAMs in 60ball FBGA
• Host interface and AMB component industry standard compliant
• MBIST & IBIST test functions
• 4 Bank architecture
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• 133.35 x 30.35 mm form factor
• RoHS compliant
• Full Module Heat Spreader
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev 1.2 / Feb. 2009
1


SK Hynix Electronic Components Datasheet

HMP512F7FFP8C-xx Datasheet

240pin Fully Buffered DDR2 SDRAM DIMMs

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www.DataSheet4U.net
1240pin Fully Buffered DDR2 SDRAM DIMMs
ORDERING INFORMATION
Part Name
Density
HMP564F7FFP8C-C4/Y5N3
HMP564F7FFP8C-C4/Y5/S5/S6D3
HMP512F7FFP8C-C4/Y5N3
HMP512F7FFP8C-C4/Y5/S5/S6D3
HMP525F7FFP4C-C4/Y5N3
HMP525F7FFP4C-C4/Y5D3
512MB
1GB
2GB
Org.
# of # of
AMB
DRAMs ranks Vendor Version
H. S
type
Height
64Mx72
9
128Mx72
18
256Mx72
36
Intel
D1
1
IDT C1
2
Intel
IDT
D1
C1
Full
Module
30.35mm
Intel
D1
2
IDT C1
Note:
*: The 16th and 17th digits stand for AMB vendor and revision.
SPEED GRADE & KEY PARAMETERS
Speed Grade
DDR2 DRAM Speed Grade
FB-DIMM Speed Grade
FB-DIMM Peak Channel Throughput
FB-DIMM Link Transfer Rate
C4 Y5
S5/6
DDR2 533 4-4-4
PC2 4200
6.4
3.2
DDR2 667 5-5-5
PC2 5300
8.0
4.0
DDR2 800 5-5-5 / 6-6-6
PC2 6400
9.6
4.8
Unit
GByte/S
GT/s
ADDRESS TABLE
Density
Org.
Ranks
SDRAMs
# of
DRAMs
# of row/bank/column Address
512MB 64M x 72
1 64Mbx8
9 14(A0~A13)/2(BA0~BA1)/10(A0~A9)
1GB 128M x 72 2 64Mbx8 18 14(A0~A13)/2(BA0~BA1)/10(A0~A9)
2GB 256M x 72 2 128Mbx4 36 14(A0~A13)/2(BA0~BA1) 11(A0~A9,A11)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
Rev 1.2 / Feb. 2009
2


Part Number HMP512F7FFP8C-xx
Description 240pin Fully Buffered DDR2 SDRAM DIMMs
Maker Hynix Semiconductor
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