HMP512F7FFP8C-xx
Overview
- 240 pin Fully Buffered ECC dual In-Line DDR2 SDRAM Module JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Built with 512Mb DDR2 SDRAMs in 60ball FBGA Host interface and AMB component industry standard compliant MBIST & IBIST test functions 4 Bank architecture OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) Programmable Burst Length 4 / 8 with both sequential and interleave mode Auto refresh and self refresh supported 8192 refresh cycles / 64ms Serial presence detect with EEPROM 133.35 x 30.35 mm form factor RoHS compliant Full Module Heat Spreader This document is a ge
