HMP564P7FFP8C-Y5 Datasheet PDF (240pin Registered DDR2 SDRAM DIMMs) | Download Hynix Semiconductor HMP564P7FFP8C-Y5

HMP564P7FFP8C-Y5 - 240pin Registered DDR2 SDRAM DIMMs

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

JEDEC standard 1.8V +/- 0.1V Power Supply VDDQ : 1.8V +/- 0.1V All inputs and outputs are compatible with SSTL_1.8 interface 4 Bank architecture Posted CAS Programmable CAS Latency 3 , 4 , 5 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination) Fully differential clock operations (CK & CK) Programmable Bu.

Datasheet Details

Part number	HMP564P7FFP8C-Y5
Manufacturer	SK Hynix
File Size	753.52 KB
Description	240pin Registered DDR2 SDRAM DIMMs
Datasheet	HMP564P7FFP8C-Y5 Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.net 240pin Registered DDR2 SDRAM DIMMs based on 512 Mb F ver. This Hynix registered Dual In-Line Memory Module (DIMM) series consists of 512Mb F ver. DDR2 SDRAMs in Fine Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb F ver. based Registered DDR2 DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. ORDERING INFORMATION Part Name HMP564P7FFP8C-Y5 HMP512R7FFP4C-E3 HMP512P7FFP4C-Y5 HMP525R7FFP4C-E3 HMP525P7FFP4C-Y5 Density 512MB 1GB 1GB 2GB 2GB Org.

Published: Sep 5, 2011 |