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HY57V281620FLTP Datasheet Synchronous Dram Memory 128mbit (8mx16bit)

Manufacturer: SK Hynix

Overview: 128Mb Synchronous DRAM based on 2M x 4Bank x16 I/O Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 1.0 1.1 Initial Draft Final Version Correct Typo Error Page10, Page12 Correct Typo Error Page 10 : The Note for the Parameter “tOH” ( 2 -> Blank ) History Draft Date Jan. 2007 Apr. 2007 July. 2007 Remark Preliminary 1.2 Oct.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface 54 Pin TSOPII (Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM, LDQM.
  • Internal four banks operation Auto refresh and self refresh 4096 Refresh cycles / 64ms - Commercial Temperature (0oC to 70oC) - Industrial Temperature (-40oC to 85oC) Operating Temperature.

More Datasheets from SK Hynix

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HY57V281620FSTP Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620FTP Synchronous DRAM Memory 128Mbit (8Mx16bit)
HY57V281620A 4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ELT Synchronous DRAM Memory
HY57V281620ELTP Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620EST Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620ET Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620ETP Synchronous DRAM Memory 128Mbit (8M x 16bit)
HY57V281620HCT (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM
HY57V281620HLT (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM

HY57V281620FLTP Distributor