HY57V28820HLT-L Datasheet PDF ((HY57V28820HC(L)T-L) 4Banks x 4M x 8bits Synchronous DRAM) | Download Hynix Semiconductor HY57V28820HLT-L

HY57V28820HLT-L - (HY57V28820HC(L)T-L) 4Banks x 4M x 8bits Synchronous DRAM

Download the HY57V28820HLT-L datasheet PDF (HY57V28820HCT included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for (hy57v28820hc(l)t-l) 4banks x 4m x 8bits synchronous dram.

Description

The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range.

f HY57V28820HC(L)T is organized as 4banks of 4,194,304x8.

Features

Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation.
Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst.
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Datasheet Details

Part number	HY57V28820HLT-L
Manufacturer	SK Hynix
File Size	382.57 KB
Description	(HY57V28820HC(L)T-L) 4Banks x 4M x 8bits Synchronous DRAM
Datasheet	HY57V28820HLT-L Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com HY57V28820HC(L)T-I 4Banks x 4M x 8bits Synchronous DRAM DESCRIPTION The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the Mobile applications which require low power consumption and extended temperature range. f HY57V28820HC(L)T is organized as 4banks of 4,194,304x8. HY57V28820HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Published: Oct 9, 2006 |