HY57V561620CLT - 4 Banks x 4M x 16Bit Synchronous DRAM
HY57V561620CLT Features
* Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch (Leaded Package or Lead Free Package) All inputs and outputs referenced to positive edge of system clock Data mask function by UD