HY57V561620FT-6 - 256M (16M x 16bit) Hynix SDRAM Memory

SK Hynix

Datasheet Details

Part number	HY57V561620FT-6
Manufacturer	SK Hynix
File Size	727.86 KB
Description	256M (16M x 16bit) Hynix SDRAM Memory
Datasheet	HY57V561620FT-6 Datasheet

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Overview

256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 4,194,304 x 16 This document is a general.

Key Features

Standard SDRAM Protocol.
Internal 4bank operation.
Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V.
All device pins are compatible with LVTTL interface.
Low Voltage interface to reduce I/O power.
8,192 Refresh cycles / 64ms.
Programmable CAS latency of 2 or 3.
Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst.
0oC ~ 70oC Operation.
Package Type : 54_Pin TSOPII (Lead Free,.

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