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HY57V56820BT Datasheet 4 Banks x 8M x 8Bit Synchronous DRAM

Manufacturer: SK Hynix

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General Description

The HY57V56820B is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

The HY57V56820B is organized as 4banks of 8,388,608x8.

The HY57V56820B is offering fully synchronous operation referenced to a positive edge of the clock.

Overview

www.DataSheet4U.com HY57V56820B(L)T 4 Banks x 8M x 8Bit Synchronous.

Key Features

  • Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM Internal four banks operation.
  • Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst.
  • - 1, 2, 4 o.

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