HY5DU28822T sdram equivalent, 2nd 128m ddr sdram.
*
*
*
*
*
*
* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) .
which requires large memory density and high bandwidth. The Hynix 128Mb DDR SDRAMs offer fully synchronous operations re.
Image gallery
Download