HY5DU561622AT Datasheet PDF ((HY5DU56xx22A(L)T) 256M-S DDR SDRAM) | Download Hynix Semiconductor HY5DU561622AT

HY5DU561622AT - (HY5DU56xx22A(L)T) 256M-S DDR SDRAM

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS).
All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable CAS latency 1.5, 2, 2.5 an.

Datasheet Details

Part number	HY5DU561622AT
Manufacturer	SK Hynix
File Size	529.85 KB
Description	(HY5DU56xx22A(L)T) 256M-S DDR SDRAM
Datasheet	HY5DU561622AT Datasheet

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Full PDF Text Transcription

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www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T 256M-S DDR SDRAM HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T DataSheet4U.com DataShee This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4/ May. 02 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Revision History 1. Revision 0.2 (Jan. 02) 1) Define Preliminary Specification 2. Revision 0.3 (Mar. 02) 1) Define IDD Specification 2) Added programmable Cas Latrency 1.5 3) Changed VREF value from min (0.49*VDDQ) & max (0.

Published: Oct 10, 2006 |