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SK Hynix Electronic Components Datasheet

HY5R128HC745 Datasheet

(HY5R1xxHCxxx) RDRAM

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Direct RDRAM
128/144Mbit (256Kx16/18x32s) Preliminary
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 128/144-Mbit Direct Rambus DRAMs (RDRAM®) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16 or 18 bits. The use of Rambus Signaling Level
www.DataSh(eReSt4LU).ctoemchnology permits 600MHz to 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's 32 banks
support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Features
Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in
power consumption versus time to transition to active
state
- Power-down self-refresh
Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
Uses Rambus Signaling Level (RSL) for up to
800MHz operation
Figure 1: Direct RDRAM uBGA Package
The 128/144-Mbit Direct RDRAMs are offered in a uBGA
package suitable for desktop as well as low-profile add-in
card and mobile applications.
Direct RDRAMs operate from a 2.5 volt supply.
Key Timing Parameters/Part Numbers
Organizationa
I/O Freq. Core Access Time
MHz
(ns)
Part
Number
256Kx16x32s
256Kx16x32s
256Kx16x32s
256Kx16x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
256Kx18x32s
600
711
800
800
600
711
800
800
600
711
800
800
53 HY5R128HC653
45 HY5R128HC745
45 HY5R128HC845
40 HY5R128HC840
53 HY5R144HC653
45 HY5R144HC745
45 HY5R144HC845
40 HY5R144HC840
53 HY5R144HMb653
45 HY5R144HM745
45 HY5R144HM845
40 HY5R144HM840
a. The “32s” designation indicates that this RDRAM core is com-
posed of 32 banks which use a “split” bank architecture.
b. The “M” indicates the mirrored package.
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1/June.00
1


SK Hynix Electronic Components Datasheet

HY5R128HC745 Datasheet

(HY5R1xxHCxxx) RDRAM

No Preview Available !

128/144Mbit (256Kx16/18x32s)
Pinouts and Definitions
Center-Bonded Devices
These tables shows the pin assignments of the center-bonded
RDRAM package. The top table is for the normal package,
and the bottom table is for the mirrored package. The
mechanical dimensions of this package are shown in a later
section. Refer to Section "Center-Bonded uBGA Package"
on page 60. ( Note : pin#1 is at the A1 position. )
Table 1: Center-Bonded Device (top view for Normal Package)
12 GND
11
www.DataSheet4U.com
10 DQA7
9 GND
8 CMD
7
6
5 SCK
4 VCMOS
3 DQA8
2
1 GND
A
DQA4
VDD
DQA5
DQA6
GND
DQA3
B
VDD
CFM
GND
DQA2
CFMN
GNDa
VDDa
DQA1
VDD
DQA0
VREF
GND
CTMN
VDD
CD
RQ5
VDD
RQ6
RQ7
GND
CTM
E
VDD
GND
RQ3
GND
RQ2
DQB0
VDD
DQB1
DQB4
VDD
DQB5
DQB7
GND
SIO1
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
DQB3
SIO0
VCMOS
DQB8
VDD
GND
F GH
J
Table 2: Center-Bonded Device (top view for Mirrored Package)
12 GND
VDD
11
10
DQA8
DQA3
DQA0
CTMN
CTM
9
VCMOS
GND
VDD
GND
GND
8
SCK
DQA6
DQA1
VREF
RQ7
7
6
5
CMD
DQA5
DQA2
VDDa
RQ6
4
GND
VDD
GND
GNDa
VDD
3
DQA7
DQA4
CFM
CFMN
RQ5
2
1 GND
VDD
A BCDE
VDD
GND
RQ4
VDD
RQ1
RQ0
GND
DQB2
DQB3
GND
DQB6
DQB8
VCMOS
SIO0
RQ2
GND
RQ3
DQB1
VDD
DQB0
DQB5
VDD
DQB4
SIO1
GND
DQB7
VDD
GND
F GH
J
2 Rev.1.1 June.00


Part Number HY5R128HC745
Description (HY5R1xxHCxxx) RDRAM
Maker Hynix Semiconductor
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