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HY5S7B6ALFP-6 - 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O

Datasheet Details

Part number HY5S7B6ALFP-6
Manufacturer SK Hynix
File Size 656.38 KB
Description 512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O
Datasheet download datasheet HY5S7B6ALFP-6 Datasheet

General Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Overview

512MBit MOBILE SDR SDRAMs based on 8M x 4Bank x16I/O Document Title 4Bank x 8M x 16bits Synchronous DRAM Revision History Revision No.

0.1 0.2 1.0 1.1 Initial Draft Inserted 166MHz Product Release Insert (Page10) DPD specification [IDD7 : 10uA min] History Draft Date Aug.

2006 Sep.

Key Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).