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HYMP112S64MP8 - DDR2 SDRAM SO-DIMM

This page provides the datasheet information for the HYMP112S64MP8, a member of the HYMP112S64MLP8 DDR2 SDRAM SO-DIMM family.

Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • 1GB (128M x 64) Unbuffered DDR2 SO - DIMM based on 128Mx8 DDR2 DDP SDRAMs JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differential clock operations (CK & /CK) Programmable CAS Latency 3 / 4 /5 supported.
  • Programmable Burst Lengt.

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Datasheet preview – HYMP112S64MP8

Datasheet Details

Part number HYMP112S64MP8
Manufacturer Hynix Semiconductor
File Size 449.33 KB
Description DDR2 SDRAM SO-DIMM
Datasheet download datasheet HYMP112S64MP8 Datasheet
Additional preview pages of the HYMP112S64MP8 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com DDR2 SDRAM SO-DIMM HYMP112S64(L)MP8 Revision History No. 0.1 History 1) Defined target spec. 2) Corrected Pin assignment table Date July 2004 Remark 128Mx64 bits This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ July 2004 1 www.DataSheet4U.com DDR2 SDRAM SO-DIMM HYMP112S64(L)MP8 DESCRIPTION 128Mx64 bits Hynix HYMP112S64MP8 series is unbuffered 200-pin double data rate 2 Synchronous DRAM Small Outline Dual In-Line Memory Modules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMP112S64MP8 series consists of eight 128Mx8 DDR2 SDRAMs in 63 ball FBGA Dual Die Pacakge(DDP)s.
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