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ICMIC

X25170 Datasheet Preview

X25170 Datasheet

SPI Serial E2PROM

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This X25170 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
ICmicTM
IC MICROSYSTEMS
16K
X25170
2K x 8 Bit
SPI Serial E 2PROM with Block Lock Protection
FEATURES
•5MHz Clock Rate
•SPI Modes (0,0 & 1,1)
•2K X 8 Bits
—32 byte page mode
•Low Power CMOS
—<1µA standby current
—<5mA active current
•2.5V To 5.5V Power Supply
•Block Lock Protection
—Protect 1/4, 1/2 or all of E2PROM array
Built-In Inadvertent Write Protection
—Power-up/power-down protection circuitry
—Write enable latch
—Write protect pin
•Self-Timed Write Cycle
—5ms write cycle time (typical)
•High Reliability
—Endurance: 100,000 cycles
—Data retention: 100 Years
—ESD protection: 2000V on all pins
•8-Lead PDlP Package
•8-Lead SOIC Package
14-Lead TSSOP Package
DESCRIPTION
The X25170 is a CMOS 16384-bit serial E2PROM,
internally organized as 2K x 8. The X25170 features a
Serial Peripheral Interface (SPI) and software protocol,
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is
controlled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25170 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, the X25170 will ignore transitions on its
inputs, thus allowing the host to service higher prior-
ity interrupts. The WP input can be used as a hardwire input
to the X25170 (disabling all write attempts to the
status register), thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25170 utilizes Xicor’s proprietary Direct Write cell,
providing a minimum endurance of 100,000 cycles and a
www.DataSheet.co.kr
minimum data retention of 100 years.
BLOCK DIAGRAM
Status
Register
SO
SI
SCK
CS
HOLD
Command
Decode
and
Control
Logic
Write
Protect
Logic
Write
Control
and
WP
Timing
Logic
Direct Writeand Block LockProtection is a trademark of Xicor, Inc.
©Xicor, Inc. 2000 Patents Pending
9900-5004.9 5/26/00 EP
X Decode
Logic
16
2K Byte
Array
16 X 256
16
16 X 256
32
32 X 256
32 8
Y Decode
Data Register
Characteristics subject to change without notice. 1 of 15
Datasheet pdf - http://www.DataSheet4U.net/




ICMIC

X25170 Datasheet Preview

X25170 Datasheet

SPI Serial E2PROM

No Preview Available !

X25170
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of
the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
It should be noted that after power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
When CS is HIGH, the X25170 is deselected and the
SO output pin is at high impedance; unless an internal
write operation is underway, the X25170 will be in the
standby power mode. CS LOW enables the X25170,
placing it in the active power mode.
Write Protect (WP)
When WP is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25170 status register are dis-
abled, but the part otherwise functions normally. When
WP is held HIGH, all functions, including nonvolatile
writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25170 status reg-
ister. If the internal write cycle has already been initi-
ated, WP going LOW will have no effect on a write.
The WP pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install
the X25170 in a system with WP pin grounded and still
be able to write to the status register. The WP pin func-
tions will be enabled when the WPEN bit is set “1”.
Pin Names
Symbol
CS
SO
SI
SCK
WP
VSS
VCC
HOLD
NC
Description
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
PIN CONFIGURATION
DIP/SOIC
CS 1
8 VCC
SO 2
7 HOLD
WP 3 X25170 6 SCK
VSS
4
5 SI
TSSOP
www.DataSheet.co.kr
CS 1
SO 2
14 VCC
13 HOLD
NC 3
12
NC 4 X25170 11
NC
NC
NC 5
10 NC
WP 6
VSS 7
9 SCK
8 SI
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume com-
munication, HOLD is brought HIGH, again while SCK
is LOW. If the pause feature is not used, HOLD should
be held HIGH at all times.
Characteristics subject to change without notice. 2 of 15
Datasheet pdf - http://www.DataSheet4U.net/


Part Number X25170
Description SPI Serial E2PROM
Maker ICMIC
Total Page 15 Pages
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