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IP101GA Datasheet Preview

IP101GA Datasheet

Fast Ethernet Transceiver

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IP101G
Data Sheet
Single Port 10/100 MII/RMII/TP/Fiber
Fast Ethernet Transceiver
(85nm/Extreme Low PW, PWMT® and EMIMT®)
Features
z 10/100Mbps IEEE 802.3/802.3u compliant
Fast Ethernet transceiver
z Supports 100Base-TX/FX Media Interface
z Supports MII/ RMII Interface
z Supports Auto MDI/MDIX function
z Power Management Tool
- APS, auto power saving while Link-off
- 802.3az, protocol based power saving
- WOL+, light traffic power saving
- PWD, force-off power saving
- Supports MII with LPI for RX and TX
- Supports RMII with LPI for RX
z Supports Base Line Wander compensation
z Supports Interrupt function
z Built in synchronization FIFO to support
jumbo frame size up to 12KB in MII mode (10KB
in RMII 100Mbps mode)
z Supports MDC and MDIO to communicate
with the MAC
z EMI Management Tool
- F/W based control
- 4 levels for mapping the difference layout
length on the PCB
z Single 3.3V power supply
z Built-in Vcore regulator
z DSP-based PHY Transceiver technology
z System Debug Assistant Tool
- 16 bit RX counter
- 9 bit RXError/CRC counter
- Isolate MII/RMII
- RX to TX Loopback
- Loopback MII/RMII
z Using either 25MHz crystal/oscillator or
50MHz oscillator REF_CLK as clock source
z Built-in 49.9ohm resistors for simplifying
BOM
z Flexible LED display
z Process: 85nm
General Description
z Package and operation temperature
IP101G: dice, 0~70
IP101GA: 48LQFP, 0~70
IP101GR: 32QFN, 0~70
IP101GRI: 32QFN, -40~85
IP101G is an IEEE 802.3/802.3u compliant
single-port Fast Ethernet Transceiver for both
100Mbps and 10Mbps operations. It supports
Auto MDI/MDIX function to simplify the network
installation and reduce the system maintenance
cost. To improve the system performance,
IP101G provides a hardware interrupt pin to
indicate the link, speed and duplex status
change. IP101G provides Media Independent
Interface (MII) or Reduced Media Independent
Interface (RMII) to connect with different types
of 10/100Mbps Media Access Controller (MAC).
IP101G is designed to use category 5
unshielded twisted-pair cable or Fiber-Optic
cables connecting to other LAN devices. A
PECL interface is supported to connect with an
external 100Base-FX fiber optical transceiver.
Except good performance, reliability, rich power
saving method and extreme low operating
current, IP101G provides a serial tool for
system designers to complete their projects
easily. They are System Debug Assistant Tool
and EMI Management Tool.
IP101G is fabricated with advanced CMOS
(85nm) technology and design is based on
IC Plus’s 5th Ethernet-PHY architecture, this
feature makes IP101G consumes very low
power. Such as in the full load operation
(100Mbps_FDX), it only takes below 0.15W.
IP101GA / IP101GR&IP101GRI are available in
48LQFP/32QFN, lead-free package.
* EMIMT: Patent under apply.
Application
NAS
Network Printers and Servers
IP Set-Top Box
IP/Smart TV
Game console
IP and Video Phone
PoE
Telecom Fiber device
1/65
Copyright © 2011, IC Plus Corp.
January 14, 2014
IP101G-DS-R01




IC Plus

IP101GA Datasheet Preview

IP101GA Datasheet

Fast Ethernet Transceiver

No Preview Available !

IP101G
Data Sheet
Table Of Contents
Table Of Contents.................................................................................................................................... 2
List of Figures .......................................................................................................................................... 4
List of Tables............................................................................................................................................ 5
Revision History....................................................................................................................................... 6
Features comparison between IP101G and IP101A/IP101AH ............................................................... 7
Transmit and Receive Data Path Block Diagram .................................................................................... 8
1 Pin diagram ...................................................................................................................................... 9
2 Dice pad information .......................................................................................................................11
3 Pin description................................................................................................................................ 12
3.1 IP101GA pin description .................................................................................................... 12
3.2 IP101GR/GRI pin description............................................................................................. 16
4 Register Descriptions ..................................................................................................................... 19
4.1 Register Page mode Control Register ............................................................................... 20
4.2 MII Registers ...................................................................................................................... 20
4.3 MMD Control Register ....................................................................................................... 30
4.4 MMD Data Register ........................................................................................................... 31
4.5 RX Counter Register.......................................................................................................... 34
4.6 LED Pin Control Register................................................................................................... 35
4.7 WOL+ Control Register...................................................................................................... 35
4.8 UTP PHY Specific Control Register ................................................................................... 38
4.9 Digital IO Pin Control Register ........................................................................................... 39
5 Function Description....................................................................................................................... 41
5.1 Major Functional Block Description ................................................................................... 41
5.1.1
Transmission Description...................................................................................... 41
5.1.2
MII and Management Control Interface ................................................................ 42
5.1.3
RMII Interface ....................................................................................................... 43
5.1.4
Flexible Clock Source ........................................................................................... 45
5.1.5
Auto-Negotiation and Related Information............................................................ 45
5.1.6
Auto-MDIX function............................................................................................... 46
5.2 PHY Address Configuration ............................................................................................... 46
5.3 Power Management Tool ................................................................................................... 47
5.3.1
Auto Power Saving Mode ..................................................................................... 47
5.3.2
IEEE802.3az EEE (Energy Efficient Ethernet) ..................................................... 48
5.3.3
Force power down ................................................................................................ 48
5.3.4
WOL+ operation mode.......................................................................................... 48
5.4 LED Mode Configuration.................................................................................................... 52
5.5 LED Blink Timing................................................................................................................ 52
5.6 Repeater Mode .................................................................................................................. 52
5.7 Interrupt.............................................................................................................................. 52
5.8 Miscellaneous .................................................................................................................... 52
5.9 Serial Management Interface............................................................................................. 53
5.10 Fiber Mode Setting............................................................................................................. 54
5.11 Jumbo Frame ..................................................................................................................... 54
6 Layout Guideline ............................................................................................................................ 55
6.1 General Layout Guideline .................................................................................................. 55
6.2 Twisted Pair recommendation............................................................................................ 55
7 Electrical Characteristics ................................................................................................................ 56
7.1 Absolute Maximum Rating ................................................................................................. 56
7.2 DC Characteristics ............................................................................................................. 56
7.3 Crystal Specifications......................................................................................................... 57
2/65
Copyright © 2011, IC Plus Corp.
January 14, 2014
IP101G-DS-R01


Part Number IP101GA
Description Fast Ethernet Transceiver
Maker IC Plus
PDF Download

IP101GA Datasheet PDF






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