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ICS844003I-01 Datasheet Preview

ICS844003I-01 Datasheet

CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844003I-01 is a 3 differential output LVDS
ICS Synthesizer designed to generate Ethernet refer-
HiPerClockS™ ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequen-
cies can be generated based on the settings of 4 frequency
select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz,
312.5MHz, 156.25MHz, and 125MHz. The 844003I-01 has 2
output banks, Bank A with 1 differential LVDS output pair and
Bank B with 2 differential LVDS output pairs.
• Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
• Using a 19.53125MHz or 25MHz crystal, the two output
banks can be independently set for 625MHz, 312.5MHz,
156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 490MHz to 680MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.56ps (typical)
The two banks have their own dedicated frequency select
pins and can be independently set for the frequencies men-
tioned above. The ICS844003I-01 uses ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps or
lower typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844003I-01 is packaged in a small
24-pin TSSOP package.
• 3.3V output supply mode
• -40°C to 85°C ambient operating temperature
PIN ASSIGNMENT
BLOCK DIAGRAM
CLK_ENA Pullup
DIV_SELA[1:0] Pullup
VCO_SEL Pullup
TEST_CLK Pulldown
0
XTAL_IN
XTAL_OUT
OSC
1
Phase
Detector
VCO
0 0 ÷1
0 1 ÷2
0 1 0 ÷3
1 1 ÷4 (default)
1
DIV_SELB0
VCO_SEL
MR
1
2
3
24 DIV_SELB1
2 3 VDDO_B
22 QB0
VDDO_A
QA0
nQA0
CLK_ENB
CLK_ENA
FB_DIV
VDDA
VDD
DIV_SELA0
4
5
6
7
8
9
10
11
12
21 nQB0
20 QB1
19 nQB1
18 XTAL_SEL
17 TEST_CLK
16 XTAL_IN
15 XTAL_OUT
14 GND
13 DIV_SELA1
ICS844003I-01
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
QA0
nQA0
XTAL_SEL Pullup
FB_DIV Pulldown
DIV_SELB[1:0] Pullup
MR Pulldown
CLK_ENB Pullup
FB_DIV
0 = ÷25 (default)
1 = ÷32
0 0 ÷2
0 1 ÷4
1 0 ÷5
1 1 ÷8 (default)
QB0
nQB0
QB1
nQB1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI-01
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2005
1




ICS

ICS844003I-01 Datasheet Preview

ICS844003I-01 Datasheet

CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

No Preview Available !

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I-01
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1,
24
2
3
4
5, 6
7
8
9
10
11
12,
13
14
15, 16
17
18
19, 20
Name
DIV_SELB0,
DIV_SELB1
VCO_SEL
MR
VDDO_A
QA0, nQA0
CLK_ENB
CLK_ENA
FB_DIV
VDDA
VDD
DIV_SELA0,
DIV_SELA1
GND
XTAL_OUT,
XTAL_IN
TEST_CLK
XTAL_SEL
nQB1, QB1
Type
Description
Input
Input
Input
Pullup
Pullup
Pulldown
Division select pin for Bank B. Default = HIGH.
LVCMOS/LVTTL interface levels. See Table 3C.
VCO select pin. When Low, the PLL is bypassed and the crystal reference
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state
of outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
Power
Output supply pin for Bank A outputs.
Ouput
Differential output pair. LVDS interface levels.
Input
Input
Input
Pullup
Pullup
Pulldown
Synchronizing clock enable for Bank B outputs. Active High output enable.
When logic HIGH, the output pair in Bank B is enabled. When logic LOW,
the QB outputs are LOW and nQB outputs are HIGH. Has an internal
pullup resistor so the default power-up state of output is enabled.
LVCMOS/LVTTL interface levels. See Figure 1.
Synchronizing clock enable for Bank A outputs. Active High output enable.
When logic HIGH, the output pair in Bank A is enabled. When logic LOW,
the QA output is LOW and nQA output is HIGH. Has an internal pullup
resistor so the default power-up state of output is enabled.
LVCMOS/LVTTL interface levels. See Figure 1.
Feedback divide select. When Low (default), the feedback divider is set
for ÷25. When HIGH, the feedback divider is set for ÷32.
LVCMOS/LVTTL interface levels. See Table 3D.
Power
Analog supply pin.
Power
Core supply pin.
Input
Pullup
Division select pin for Bank A. Default = HIGH.
LVCMOS/LVTTL interface levels. See Table 3C.
Power
Power supply ground.
Input
Input
Input
Pulldown
Pullup
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is
the input. XTAL_IN is also the overdrive pin if you want to overdrive the
crystal circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
pull to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected
by default. LVCMOS/LVTTL interface levels.
Output
Differential output pair. LVDS interface levels.
21, 22 nQB0, QB0 Output
Differential output pair. LVDS interface levels.
23
VDDO_B
Power
Output supply pin for Bank B outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
844003AGI-01
Test Conditions
Minimum
www.icst.com/products/hiperclocks.html
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
REV. A MAY 31, 2005
2


Part Number ICS844003I-01
Description CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Maker ICS
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