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ICS844003I Datasheet Preview

ICS844003I Datasheet

CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS844003I is a 3 differential output LVDS
ICS Synthesizer designed to generate Ethernet refer-
HiPerClockS™ ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from ICS. Using a 31.25MHz or
26.041666MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the settings of 4 fre-
quency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]):
625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003I
has 2 output banks, Bank A with 1 differential LVDS output
pair and Bank B with 2 differential LVDS output pairs.
The two banks have their own dedicated frequency se-
lect pins and can be independently set for the frequen-
cies mentioned above. The ICS844003I uses ICS’ 3rd gen-
eration low phase noise VCO technology and can achieve
1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS844003I is packaged
in a small 24-pin TSSOP package.
BLOCK DIAGRAM
CLK_ENA Pullup
DIV_SELA[1:0]
VCO_SEL Pullup
TEST_CLK Pulldown
0
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL Pullup
1
FB_DIV Pulldown
DIV_SELB[1:0]
MR Pulldown
CLK_ENB Pullup
Phase
Detector
VCO
560-700MHz
FB_DIV
0 = ÷20 (default)
1 = ÷24
FEATURES
• Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
• Using a 31.25MHz or 26.041666MHz crystal, the two
output banks can be independently set for 625MHz,
312.5MHz, 156.25MHz or 125MHz
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 560MHz to 700MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.63ps (typical)
• 3.3V output supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
0 0 ÷1
0 1 ÷2 (default)
0 1 0 ÷4
1 1 ÷5
1
PIN ASSIGNMENT
DIV_SELB0
VCO_SEL
MR
1
2
3
24 DIV_SELB1
2 3 VDDO_B
22 QB0
VDDO_A
QA0
nQA0
CLK_ENB
CLK_ENA
FB_DIV
VDDA
VDD
DIV_SELA0
4
5
6
7
8
9
10
11
12
21 nQB0
20 QB1
19 nQB1
18 XTAL_SEL
17 TEST_CLK
16 XTAL_IN
15 XTAL_OUT
14 GND
13 DIV_SELA1
ICS844003I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
QA0
nQA0
0 0 ÷1
0 1 ÷2
1 0 ÷4 (default)
1 1 ÷5
QB0
nQB0
QB1
nQB1
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI
www.icst.com/products/hiperclocks.html
REV. B AUGUST 25, 2005
1




ICS

ICS844003I Datasheet Preview

ICS844003I Datasheet

CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

No Preview Available !

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844003I
FEMTOCLOCKS™CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1
24
DIV_SELB0
DIV_SELB1
Input
Pulldown
Division select pin for Bank B. Default = Low.
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference
2
VCO_SEL
Input
Pullup
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
3 MR Input Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state of
outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
4
VDDO_A
Power
5, 6 QA0, nQA0 Ouput
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH,
7
CLK_ENB
Input
Pullup
the output pairs on Bank B are enabled. When logic LOW, the output pairs
are in a high impedance state. Has an internal pullup resistor so the default
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH,
8
CLK_ENA
Input
Pullup
the output pair in Bank A is enabled. When logic LOW, the output pair is in
a high impedance state. Has an internal pullup resistor so the default
power-up state of output is enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
9
FB_DIV
Input Pulldown for ÷20. When HIGH, the feedback divider is set for ÷24.
LVCMOS/LVTTL interface levels.
10 V
Power
DDA
Analog supply pin.
11 VDD Power
Core supply pin.
12
13
DIV_SELA0
DIV_SELA1
Input
Pullup
Division select pin for Bank A. Default = HIGH.
LVCMOS/LVTTL interface levels.
14
GND
Power
Power supply ground.
15, 16
17
18
XTAL_OUT,
XTAL_IN
TEST_CLK
XTAL_SEL
Input
Input
Input
Pulldown
Pullup
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal
circuit with a single-ended reference clock.
Single-ended reference clock input. Has an internal pulldown resistor to
pull to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected
by default. LVCMOS/LVTTL interface levels.
19, 20 nQB1, QB1 Output
Differential output pair. LVDS interface levels.
21, 22 nQB0, QB0 Output
Differential output pair. LVDS interface levels.
23 V
Power
DDO_B
Output supply pin for Bank B outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLDOWN
RPULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
844003AGI
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
www.icst.com/products/hiperclocks.html
REV. B AUGUST 25, 2005
2


Part Number ICS844003I
Description CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Maker ICS
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