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ICS844004I Datasheet Preview

ICS844004I Datasheet

CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I
FEMTOCLOCKS™CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS844004I is a 4 output LVDS Synthesizer
ICS optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocksTM family of high performance clock
solutions from ICS. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz
and 53.125MHz. The ICS844004I uses ICS’ 3rd generation
low phase noise VCO technology and can achieve <1ps
typical rms phase jitter, easily meeting Fibre Channel jitter
requirements. The ICS844004I is packaged in a small 24-pin
TSSOP package.
FEATURES
• Four LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 156.25MHz, 106.25MHz, 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637KHz - 10MHz): 0.65ps (typical)
• Full 3.3V or 2.5V supply modes
• -40°C to 85°C ambient operating temperature
FREQUENCY SELECT FUNCTION TABLE
Input
Frequency
(MHz)
26.5625
F_SEL1
Inputs
F_SEL0
M Divider
Value
N Divider
Value
M/N Divider
Value
Output
Frequency
(MHz)
0 0 24
3
8 212.5
26.5625
0
1
24
4
6 159.375
26.5625
1
0
24
6
4 106.25
26.5625
1
1
24
12
2 53.125
26.04166
0
1
24
4
6 156.25
23.4375
0
0
24
3
8 187.5
BLOCK DIAGRAM
F_SEL[1:0] Pulldown
nPLL_SEL Pulldown
TEST_CLK Pulldown
26.5625MHz
XTAL_IN
OSC
XTAL_OUT
nXTAL_SEL Pulldown
1
0
2
Phase
Detector
VCO
637.5MHz
(w/26.5625MHz
Reference)
1
0
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1 1 ÷12
M = 24 (fixed)
MR Pulldown
PIN ASSIGNMENT
nQ1
Q1
VDDo
Q0
nQ0
MR
nPLL_SEL
nc
VDDA
F_SEL0
VDD
F_SEL1
1
2
3
4
5
6
7
8
9
10
11
12
24 nQ2
23 Q2
2 2 VDDO
21 Q3
20 nQ3
19 GND
18 nc
17 nXTAL_SEL
16 TEST_CLK
15 GND
14 XTAL_IN
13 XTAL_OUT
ICS844004I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Q0 Top View
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI
www.icst.com/products/hiperclocks.html
REV. A JUNE 15, 2005
1




ICS

ICS844004I Datasheet Preview

ICS844004I Datasheet

CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER

No Preview Available !

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844004I
FEMTOCLOCKS™CRYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number Name
Type
Description
1, 2 nQ1, Q1 Output
Differential output pair. LVDS interface levels.
3, 22
4, 5
VDDO
Q0, nQ0
Power
Ouput
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
6
MR
Input
Pulldown
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and TEST_CLK as input to the dividers. When
7 nPLL_SEL Input Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
8, 18
nc Unused
No connect.
9
10, 12
VDDA
F_SEL0,
F_SEL1
Power
Analog supply pin.
Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
11
13, 14
VDD
XTAL_OUT,
XTAL_IN
Power
Input
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
15, 19
GND
Power
Power supply ground.
16 TEST_CLK Input Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or TEST_CLK inputs as the the PLL Reference
17 nXTAL_SEL Input Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH.
LVCMOS/LVTTL interface levels.
20, 21 nQ3, Q3 Output
Differential output pair. LVDS interface levels.
23, 24 Q2, nQ2 Output
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
kΩ
844004AGI
www.icst.com/products/hiperclocks.html
2
REV. A JUNE 15, 2005


Part Number ICS844004I
Description CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Maker ICS
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