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ICS844101I-312 Datasheet Preview

ICS844101I-312 Datasheet

CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844101I-312
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
GENERAL DESCRIPTION
The ICS844101I-312 is a low phase-noise
ICS frequency margining synthesizer and is a mem-
HiPerClockS™ ber of the HiPerClock S™ family of high perfor-
mance clock solutions from ICS. In the default
mode, the device nominally generates a
312.5MHz LVDS output clock signal from a 25MHz crystal
input. There is also a frequency margining mode available
where the device can be programmed, using the serial in-
terface, to vary the output frequency up or down from nomi-
nal in 2% steps. The ICS844101I-312 is provided in a 16-
pin TSSOP.
FEATURES
• One 312.5MHz nominal LVDS output
• Selectable crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal or LVCMOS single-ended
input
• Output frequency can be varied in 2% steps ± from nominal
• VCO range: 560MHz - 690MHz
• RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz-20MHz): 0.52ps (typical)
• Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-complaint
packages
BLOCK DIAGRAM
OE Pullup
CLK Pulldown
25MHz
XTAL_IN
OSC
XTAL_OUT
SEL Pulldown
1
0
S_CLOCK
S_DATA
S_LOAD
MODE
Pulldown
Pulldown
Pulldown
Pulldown
÷P
Phase
VCO
Detector
560 - 690MHz
÷M
Serial Control
÷N
PIN ASSIGNMENT
GND
S_LOAD
S_DATA
Q S_CLOCK
SEL
nQ OE
VDDA
VDD
1
2
3
4
5
6
7
8
16 MODE
1 5 VDDO
14 Q
13 nQ
12 GND
11 CLK
10 XTAL_OUT
9 XTAL_IN
ICS844101I-312
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844101AGI-312
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 28, 2005
1




ICS

ICS844101I-312 Datasheet Preview

ICS844101I-312 Datasheet

CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

No Preview Available !

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS844101I-312
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS844101I-312 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 25MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the oscilla-
tor is fed into the pre-divider. In frequency margining mode,
the 25MHz crystal frequency is divided by 2 and a 12.5MHz
reference frequency is applied to the phase detector. The
VCO of the PLL operates over a range of 560MHz to
690MHz. The output of the M divider is also applied to the
phase detector.
some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an
output divider prior to being sent to the LVPECL output
buffer. The divider provides a 50% output duty cycle. The
relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency is
provided in Table 1. When changing back from frequency
margining mode to nominal mode, the device will return to
the default nominal configuration that will provide
312.5MHz output frequency.
The default mode for the ICS844101I-312 is 312.5MHz
output frequency using a 25MHz crystal. The output fre-
quency can be changed by placing the device into the
margining mode using the mode pin and using the serial
interface to program the M feedback divider. Frequency
margining mode operation occurs when the MODE input
is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference fre-
quency by adjusting the VCO control voltage. Note that for
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
Serial operation occurs when S_LOAD is HIGH. Serial data
can be loaded in either the default mode or the frequency
margining mode. The 6-bit shift register is loaded by sam-
pling the S_DATA bits with the rising edge of S_CLOCK.
After shifting in the 6-bit M divider value, S_LOAD is
transitioned from HIGH to LOW which latches the contents of
the shift-register into the M divider control register. When
S_LOAD is LOW, any transitions of S_CLOCK or S_DATA
are ignored.
XTAL Pre-Divider
Reference
Feedback M-Data
(MHz) (P) Frequency (MHz) Divider (M) (Binary)
25 2
12.5 45 101101
VCO Output
Output
(MHz) Divider (N) Frequency (MHz)
562.5
2
281.25
%
Change
-10.0
25 2
12.5
46 101110 575
2
287.5
-8.0
25 2
12.5
47 101111 587.5 2
293.75
-6.0
25 2
12.5
48 110000 600
2
300 -4.0
25 2
12.5
49 110001 612.5 2
306.25
-2.0
25 2
12.5
50 110010 625
2
312.5
0
25 2
12.5
51 110011 637.5 2
318.75
2.0
25 2
12.5
52 110100 650
2
325 4.0
25 2
12.5
53 110101 662.5 2
331.25
6.0
25 2
12.5
54 110110 675
2
337.5
8.0
25 2
12.5
55 110111 687.5 2
343.75
10.0
SERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
844101AGI-312
M5 M4 M3 M2 M1 M0
tt
SH
t
S
Time
FIGURE 1. SERIAL LOAD OPERATIONS
www.icst.com/products/hiperclocks.html
2
REV. A NOVEMBER 28, 2005


Part Number ICS844101I-312
Description CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Maker ICS
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