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ICS8442I Datasheet Preview

ICS8442I Datasheet

CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

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Integrated
Circuit
Systems, Inc.
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
ICS
HiPerClockS™
The ICS8442I is a general purpose, dual output
Crystal-to-Differential LVDS High Frequency
Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
Dual differential LVDS outputs
Selectable crystal oscillator interface or
LVCMOS/LVTTL TEST_CLK
ICS. The ICS8442I has a selectable TEST_CLK Output frequency range: 31.25MHz to 700MHz
or crystal input. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to LVDS levels. The Crystal input frequency range: 10MHz to 25MHz
VCO operates at a frequency range of 250MHz to 700MHz. VCO range: 250MHz to 700MHz
The VCO frequency is programmed in steps equal to the value
of the input reference or crystal frequency. The VCO and output Parallel or serial interface for programming counter
frequency can be programmed using the serial or parallel
and output dividers
interface to the configuration logic. The low phase noise RMS period jitter: 3.5ps (typical)
characteristics of the ICS8442I makes it an ideal clock source
for Gigabit Ethernet and Sonet applications.
Cycle-to-cycle jitter: 18ps (typical)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
OSC
0
1
MR
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
PLL
PHASE DETECTOR
÷1
VCO
÷2
0 ÷4
÷M 1 ÷8
CONFIGURATION
INTERFACE
LOGIC
PIN ASSIGNMENT
FOUT0
nFOUT0
FOUT1
nFOUT1
M5
M6
M7
M8
N0
N1
nc
GND
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 ICS8442I 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
XTAL_OUT
TEST_CLK
XTAL_SEL
VDDA
S_LOAD
S_DATA
S_CLOCK
MR
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8442AYI
www.icst.com/products/hiperclocks.html
1
REV. C MAY 10, 2005




ICS

ICS8442I Datasheet Preview

ICS8442I Datasheet

CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER

No Preview Available !

Integrated
Circuit
Systems, Inc.
ICS8442I
700MHZ, CRYSTAL OSCILLATOR-TO-DIFFERENTIAL
LVDS FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 25MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 5, NOTE 1.
The ICS8442I features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a
range of 250MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVDS output buffers.The divider provides a 50% output duty cycle.
The programmable features of the ICS8442I support two in-
put modes to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode,
the nP_LOAD input is initially LOW. The data on inputs M0
through M8 and N0 and N1 is passed directly to the M divider
and N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a
serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a spe-
cific default state that will automatically occur during power-
up. The TEST output is LOW when operating in the parallel
input mode. The relationship between the VCO frequency, the
crystal frequency and the M divider is defined as follows:
fVCO = fxtal x M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
25MHz reference are defined as 10 M 28. The frequency
out is defined as follows:
FOUT = fVCO = fxtal x M
NN
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output di-
vider when S_LOAD transitions from LOW-to-HIGH. The M
divide and N output divide values are latched on the HIGH-to-
LOW transition of S_LOAD. If S_LOAD is held HIGH, data at
the S_DATA input is passed directly to the M divider and N
output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1 T0
TEST Output
00
LOW
01
S_Data, Shift Register Input
10
Output of M divider
11
CMOS FOUT
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
SERIAL LOADING
T1 T0 *NULL N1 N0 M8
tt
SH
M7 M6 M5 M4
M3 M2 M1 M0
M, N
PARALLEL LOADING
t
S
nP_LOAD
tt
SH
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8442AYI
www.icst.com/products/hiperclocks.html
2
REV. C MAY 10, 2005


Part Number ICS8442I
Description CRYSTAL OSCILLATOR-TO-DIFFERENTIAL LVDS FREQUENCY SYNTHESIZER
Maker ICS
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ICS8442I Datasheet PDF





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