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ICS951413 Datasheet Preview

ICS951413 Datasheet

Programmable System Clock Chip

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Integrated
Circuit
Systems, Inc.
ICS951413
Programmable System Clock Chip for ATI RS400 P4TM-based Systems
Recommended Application:
ATI RS400 systems using Intel P4TM processors
Output Features:
• 6 - Pairs of SRC/PCI Express* clocks
• 2 - Pairs of programmable SRC/PCI Express (ATIG)
clocks
• 3 - Pairs of Intel P4 clocks
• 3 - 14.318 MHz REF clocks
• 1 - 48MHz USB clock
• 1 - 33 MHz PCI clock seed
Features/Benefits:
• 2 - Programmable Clock Request pins for SRC clocks
• Supports CK410 or CK409 frequency table mapping
• Spread Spectrum for EMI reduction
• Outputs may be disabled via SMBus
• External crystal load capacitors for maximum
frequency accuracy
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter <125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Functionality - (CK410# = 0)
FS_C1 FS_B1 FS_A1
CPU
MHz
SRC
MHz
PCI
MHz
0 0 266.66 100.00 33.33
0 1 133.33 100.00 33.33
1 0 200.00 100.00 33.33
1 166.66 100.00 33.33
0 0 333.33 100.00 33.33
1 1 100.00 100.00 33.33
1 0 400.00 100.00 33.33
1 RESERVED
REF USB
MHz MHz
14.318 48.000
14.318 48.000
14.318 48.000
14.318 48.000
14.318 48.000
14.318 48.000
14.318 48.000
14.318 48.000
Functionality - (CK410# = 1)
FS_C1
Byte6 FS_B1 FS_A1
CPU
MHz
bit5
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
0 0 100.00 100.00 33.33 14.318 48.000
0 1 0 200.00 100.00 33.33 14.318 48.000
0 1 133.33 100.00 33.33 14.318 48.000
1 1 166.67 100.00 33.33 14.318 48.000
0 0 200.00 100.00 33.33 14.318 48.000
1 1 0 400.00 100.00 33.33 14.318 48.000
0 1 266.67 100.00 33.33 14.318 48.000
1 1 333.33 100.00 33.33 14.318 48.000
1. FS_C, FS_B and FS_A are low-threshold inputs. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
X1 1
X2 2
VDD48 3
USB_48MHz 4
GND 5
VTT_PWRGD#/PD 6
SCLK 7
SDATA 8
**FS_C 9
**CLKREQA# 10
**CLKREQB# 11
SRCCLKT7 12
SRCCLKC7 13
VDDSRC 14
GNDSRC 15
SRCCLKT6 16
SRCCLKC6 17
SRCCLKT5 18
SRCCLKC5 19
GNDSRC 20
VDDSRC 21
SRCCLKT4 22
SRCCLKC4 23
SRCCLKT3 24
SRCCLKC3 25
GNDSRC 26
ATIGCLKT1 27
ATIGCLKC1 28
56 VDDREF
55 GND
54 **FS_A/REF0
53 **FS_B/REF1
52 **TEST_SEL/REF2
51 VDDPCI
50 **CK410#/PCICLK0
49 GNDPCI
48 *CPU_STOP#
47 CPUCLKT0
46 CPUCLKC0
45 VDDCPU
44 GNDCPU
43 CPUCLKT1
42 CPUCLKC1
41 CPUCLKT2_ITP
40 CPUCLKC2_ITP
39 VDDA
38 GNDA
37 IREF
36 GNDSRC
35 VDDSRC
34 SRCCLKT0
33 SRCCLKC0
32 VDDATI
31 GNDATI
30 ATIGCLKT0
29 ATIGCLKC0
Note: Pins preceeded by '**' have a 120 Kohm Internal Pull Down resistor
Pins preceeded by '*' have a 120 Kohm Internal Pull Up resistor
56-pin SSOP & TSSOP
0929C—03/07/05
*Other names and brands may be claimed as the property of others.




ICS

ICS951413 Datasheet Preview

ICS951413 Datasheet

Programmable System Clock Chip

No Preview Available !

www.DataSheet4U.com
Integrated
Circuit
Systems, Inc.
ICS951413
Pin Description
PIN #
1
2
3
4
5
PIN NAME
X1
X2
VDD48
USB_48MHz
GND
6 VTT_PWRGD#/PD
7 SCLK
8 SDATA
9 **FS_C
10 **CLKREQA#
11 **CLKREQB#
12 SRCCLKT7
13 SRCCLKC7
14 VDDSRC
15 GNDSRC
16 SRCCLKT6
17 SRCCLKC6
18 SRCCLKT5
19 SRCCLKC5
20 GNDSRC
21 VDDSRC
22 SRCCLKT4
23 SRCCLKC4
24 SRCCLKT3
25 SRCCLKC3
26 GNDSRC
27 ATIGCLKT1
28 ATIGCLKC1
PIN
TYPE
DESCRIPTION
IN Crystal input, Nominally 14.318MHz.
OUT Crystal output, Nominally 14.318MHz
PWR Power pin for the 48MHz output.3.3V
OUT 48.00MHz USB clock
PWR Ground pin.
Vtt_PwrGd# is an active low input used to determine when latched inputs
IN are ready to be sampled. PD is an asynchronous active high input pin
used to put the device into a low power state. The internal clocks, PLLs
and the crystal oscillator are stopped.
IN Clock pin of SMBus circuitry, 5V tolerant.
I/O Data pin for SMBus circuitry, 5V tolerant.
IN Frequency select latch input pin
Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1:
Frequency will transition to a preprogrammed value in the I2c. / Output
IN enable for PCI Express (SRC) outputs. SMBus selects which outputs are
controlled.
0 = enabled, 1 = tri-stated
Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1:
Frequency will transition to a preprogrammed value in the I2c. / Output
IN enable for PCI Express (SRC) outputs. SMBus selects which outputs are
controlled.
0 = enabled, 1 = tri-stated
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Supply for SRC clocks, 3.3V nominal
PWR Ground pin for the SRC outputs
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Ground pin for the SRC outputs
PWR Supply for SRC clocks, 3.3V nominal
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR Ground pin for the SRC outputs
OUT True clock of differential SRC clock pair.
OUT Complementary clock of differential SRC clock pair.
0929C—03/07/05
2


Part Number ICS951413
Description Programmable System Clock Chip
Maker ICS
Total Page 23 Pages
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