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ICS97ULP845A Datasheet Preview

ICS97ULP845A Datasheet

1.8V Low-Power Wide-Range Frequency Clock Driver

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Integrated
Circuit
Systems, Inc.
ICS97UL P 8 45A
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application:
• DDR2 Memory Modules / Zero Delay Buffer Fan Out
• Provides complete DDR DIMM logic solution
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 5 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps
• Half-period jitter: 60ps
• CYCLE - CYCLE jitter 40ps
• OUTPUT - OUTPUT skew: 40ps
Pin Configuration
12 3 4 5
A
B
C
D
E
F
28-Ball BGA
Top View
Block Diagram
OE
OS
AVDD
Powerdown
Control and
Test Logic
LD* or OE
LD* PLL bypass
CLK_INT
CLK_INC
10K-100k
GND
PLL
FB_INT
FB_INC
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
1109D—06/19/07
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
Ball Assignments
12
A CLKT0 CLKC0
B CK_INT
C CK_INC
VDD
OE
D AGND
GND
E AVDD
GND
3
CLKC1
NB
VDD
VDD
NB
4
CLKT1
5
FB_INT
VDD FB_INC
OS FB_OUTC
GND FB_OUTT
GND
CLKT2
FB_OUTT
FB_OUTC
F
CLKC4
CLKT4
CLKC3
CLKT3
CLKC2




ICS

ICS97ULP845A Datasheet Preview

ICS97ULP845A Datasheet

1.8V Low-Power Wide-Range Frequency Clock Driver

No Preview Available !

ICS97UL P 8 45A
Pin Descriptions
Terminal
Name
AGND
AVDD
CLK_INT
CLK_INC
FB_INT
FB_INC
FB_OUTT
FB_OUTC
OE
OS
GND
VDDQ
CLKT[0:4]
CLKC[0:4]
NB
Description
Analog Ground
Analog power
Clock input with a (10K-100K Ohm) pulldown resistor
Complentary clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Complementary feedback clock input
Feedback clock output
Complementary feedback clock output
Output Enable (Asynchronous)
Output Select (tied to GND or VDDQ)
Ground
Logic and output power
Clock outputs
Complementary clock outputs
No ball
Electrical
Characteristics
Ground
1.8 V nominal
Differential input
Differential input
Differential input
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
1.8V nominal
Differential outputs
Differential outputs
The PLL clock buffer, ICS97ULP845A, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and
output levels. Package options include a plastic 28-ball VFBGA.
ICS97ULP845A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five
differential pair of clock outputs (CLKT[0:4], CLKC[0:4]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or VDDQ.When OS is high, OE will function as described above.When
OS is low, OE has no effect on CLKT3/CLKC3 (they are free running in addition to FB_OUTT/FB_OUTC).When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF.When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time tSTAB.
The PLL in ICS97ULP845A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:4], CLKC[0:4]).
ICS97ULP845A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
1109D—06/19/07
2


Part Number ICS97ULP845A
Description 1.8V Low-Power Wide-Range Frequency Clock Driver
Maker ICS
Total Page 12 Pages
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