ICS97ULP845A Description
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ICS97ULP845A Key Features
- Low skew, low jitter PLL clock driver
- 1 to 5 differential clock distribution (SSTL_18)
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- Auto PD when input signal is at a certain logic state
- Period jitter: 40ps
- Half-period jitter: 60ps
- CYCLE jitter 40ps
- OUTPUT
- OUTPUT skew: 40ps