ICS97ULP845A
Description
/Features
:
- Low skew, low jitter PLL clock driver
- 1 to 5 differential clock distribution (SSTL_18)
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- Auto PD when input signal is at a certain logic state
Switching Characteristics:
- Period jitter: 40ps
- Half-period jitter: 60ps
- CYCLE
- CYCLE jitter 40ps
- OUTPUT
- OUTPUT skew: 40ps
Pin Configuration
12 3 4 5 A B C D E F
28-Ball BGA
Top View
Block Diagram
OS AVDD
Powerdown Control and Test Logic
LD- or OE
LD- PLL bypass
CLK_INT CLK_INC
10K-100k GND
FB_INT FB_INC
- The Logic Detect (LD) powers down the device when a logic low is applied to both CLK_INT and CLK_INC.
1109D- 06/19/07
CLKT0 CLKC0
CLKT1 CLKC1
CLKT2...
