16-bit high-performance CMOS Dynamic Random Access Memories.
.ast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word.
Key Features
make the IC41C16105 and IC41LV16105 ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral.
Full PDF Text Transcription for IC41C16105 (Reference)
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IC41C16105. For precise diagrams, and layout, please refer to the original PDF.
IC41C16105 IC41LV16105 .EATURES 1M x 16 (16-MBIT) DYNAMIC RAM WITH .AST PAGE MODE TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms...
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nputs and outputs; tristate I/O Refresh Interval: 1,024 cycles/16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden JEDEC standard pinout Single power supply: 5V ± 10% (IC41C16105) 3.3V ± 10% (IC41LV16105) Byte Write and Byte Read operation via two CAS Industrail temperature range -40oC to 85oC DESCRIPTION The 1+51 IC41C16105 and IC41LV16105 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. .ast Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IC41C16105
IC41C16105 Datasheet
