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ICS544-01 Datasheet Preview

ICS544-01 Datasheet

Clock Divider

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PRELIMINARY INFORMATION
ICS544-01
Clock Divider
Description
The ICS544-01 is crystal oscillator module IC with
divide by 512 frequency output. It employs a 16.777216
MHz fundamental frequency crystal source oscillator to
generate 32.768 kHz output crystal oscillator output. In
addition a divide by 256, 64 and 32 options also
provided through select pins. The chip has an OE pin
that tri-states the output and stops the oscillator
circuits.
The ICS544-01 is a member of ICS’ ClockBlocksTM
family of clock building blocks. See the ICS541 and
ICS542 for other clock dividers, and the ICS501, 502,
511, 512, and 525 for clock multipliers.
Features
Packaged in 8-pin SOIC or die
Available in Pb-free package
ICS’ lowest cost clock divider
Easy to use with other generators and buffers
Input clock frequency up to 156 MHz
Output clock duty cycle of 45/55
Output Enable
Advanced, low-power CMOS process
Operating voltage of 2.25 V to 3.6 V
Does not degrade phase noise - no PLL
Available in industrial temperature range
Block Diagram
VDD
S1, S0 (1:0)
X1/ICLK
16.777216
MHz clock
or crystal
input
X2
Optional tuning
capacitors
Divider and
Selection
Circuitry
/32, /64
/256, /512,
CLK1
GND
OE
MDS 544M-01 A
1
Revision 041505
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com




ICST

ICS544-01 Datasheet Preview

ICS544-01 Datasheet

Clock Divider

No Preview Available !

PRELIMINARY INFORMATION
Pin Assignment
X1/ I CLK
X2
GND
S0
1
2
3
4
8 S1
7 VDD
6 OE
5 CLK
8-pin (150 mil) SOIC
Clock Divider Table
S1 S0
00
CLK
Input/32
01
Input/64
10
Input/256
11
Input/512
0 = connect directly to ground
1 = connect directly to VDD
ICS544-01
Clock Divider
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
Pin
Name
X1/ICLK
X2
GND
S0
CLK
OE
VDD
S1
Pin
Type
XI
Xo
Power
Input
Output
Input
Power
Input
Pin Description
Crystal or Clock input.
Connect to crystal for crystal input and leave open for clock input.
Connect to ground.
Select 0 for output clock. Connect to GND or VDD, per divider table above.
Internal pull-up resistor.
Clock output per table above.
Output Enable.Tri-states output clock when low. Also shuts down the oscillator
circuit. Internal pull-up resistor. OE=1 normal operation.
Connect to 2.25 V to 3.6 V.
Select 1 for output clock. Connect to GND or VDD, per divider table above.
Internal pull-up resistor.
External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50trace (a
commonly used trace impedance), place a 33resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20.
On chip capacitors- Crystal capacitors should be
connected from pins X1 to ground and X2 to ground to
optimize the initial accuracy. The value (in pf) of these
crystal caps equal (CL-12)*2 in this equation,
CL=crystal load capacitance in pf. For example, for a
crystal with a 16 pF load cap, each external crystal cap
would be 8 pF. [(16-12)x2]=8.
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS544-01 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the PCB ground plane.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
MDS 544M-01 A
2
Revision 041505
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com


Part Number ICS544-01
Description Clock Divider
Maker ICST
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