Description
The ICS557-08 is a 2:1 multiplexer chip that allows the user to select one of the two HCSL (Host Clock Signal Level) or LVDS input pairs and fan out to one pair of differential HCSL or LVDS outputs.
Features
- Packaged in 16-pin TSSOP Available in Pb (lead) free package Operating voltage of 3.3 V Low power consumption Input clock frequency of up to 200 MHz for HCSL and up to 100 MHz for LVDS.
- Jitter 60 ps (cycle-to-cycle)
Block Diagram
VDD 3
OE
IN1 IN1 IN2 IN2 CLK MUX 2 to 1 CLK
3 SEL GND PD
Rr (IREF)
MDS 557-08 C I n t e gra te d C i r c u i t S y s t e m s.
- 1
525 Race Stre et, San Jo se, CA 9 5126.
- Revision 021606 te l (40.
ICS557-08_ICST.pdf
