ICS853001 Key Features
- 1:1 Differential LVPECL-to-LVPECL / ECL buffer
- 1 LVPECL clock output pair
- 1 Differential LVPECL PCLK, nPCLK input pair
- PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML
- Maximum output frequency: >2.5GHz
- Part-to-part skew: 100ps (maximum)
- Propagation delay: 500ps (maximum)
- Additive phase jitter, RMS: 0.03ps (typical)
- LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V, VEE = 0V
- ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V