ICS853013 Key Features
- Two differential LVPECL / ECL bank outputs
- Two differential LVPECL clock input pairs
- PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
- Output frequency: >2GHz (typical)
- Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input
- Output skew: 40ps (maximum)
- Part-to-part skew: 250ps (maximum)
- Propagation delay: 570ps (maximum)
- Additive phase jitter, RMS: 0.03ps (typical)
- LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V