ICS85310I-31 ICST Datasheet

ICS85310I-31 Key Features

• 2 differential 2.5V/3.3V LVPECL / ECL bank outputs
• 2 differential clock input pairs
• CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 700MHz
• Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLKx input
• Output skew: 25ps (typical)
• Part-to-part skew: 270ps (typical)
• Propagation delay: 1.7ns (typical)
• Additive phase jitter, RMS: <0.13ps (typical)
• LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V